mrg ab5dd47182 Ptx is in microns if lvs_lib exists		2020-04-03 14:06:56 -07:00
..
contact.py	Update contact well support.	2020-02-05 18:21:01 +00:00
custom_cell_properties.py	sense_amp: Allow custom pin names	2020-02-17 15:20:12 +01:00
delay_data.py	…
design.py	Add general well_extend_active DRC in design class.	2020-02-05 18:22:22 +00:00
geometry.py	Add instance center location	2020-02-28 18:24:09 +00:00
graph_util.py	…
hierarchy_design.py	Add optional lvs_lib netlists for LVS usage (sp_lib is for simulation)	2020-04-03 13:39:54 -07:00
hierarchy_layout.py	Min area only for multiple layers	2020-03-26 13:05:02 -07:00
hierarchy_spice.py	Ptx is in microns if lvs_lib exists	2020-04-03 14:06:56 -07:00
lef.py	…
pin_layout.py	added purposes to addText(), removed reference to specific tech from gdsMill	2020-02-19 16:26:52 -08:00
power_data.py	…
route.py	…
utils.py	s8 gdsless netlist only working up to dff array	2020-02-09 21:37:09 -08:00
vector.py	Merge branch 'tech_migration' into dev	2020-01-25 12:03:56 -08:00
verilog.py	…
wire.py	…
wire_path.py	…
wire_spice_model.py	…