jcirimel 7038fad930 s8 gdsless netlist only working up to pdriver

2020-02-09 23:10:33 -08:00

..

bank_select.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

bank.py

add simple sram sizing for netlist only

2020-02-06 12:10:49 +00:00

bitcell_array.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

bitcell_base_array.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

control_logic.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

custom_module_properties.py

s8 gdsless netlist only working up to pdriver

2020-02-09 23:10:33 -08:00

delay_chain.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

dff_array.py

add custom module file, make dff clk pin dynamic

2020-02-04 23:35:06 -08:00

dff_buf_array.py

s8 gdsless netlist only working up to pdriver

2020-02-09 23:10:33 -08:00

dff_buf.py

s8 gdsless netlist only working up to pdriver

2020-02-09 23:10:33 -08:00

dff_inv_array.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

dff_inv.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

dff.py

add custom module file, make dff clk pin dynamic

2020-02-04 23:35:06 -08:00

dummy_array.py

Fix base bitcell syntax error. Remove some unused imports.

2020-01-30 01:58:30 +00:00

hierarchical_decoder.py

Pgates are 8 M1 high by default. Port data is bitcell height.

2020-01-30 03:34:04 +00:00

hierarchical_predecode2x4.py

Removed all unused analytical delay functions.

2019-08-06 17:09:25 -07:00

hierarchical_predecode3x8.py

Removed all unused analytical delay functions.

2019-08-06 17:09:25 -07:00

hierarchical_predecode.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

module_type.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

multibank.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

port_address.py

Add separate well design rules.

2020-01-23 19:43:41 +00:00

port_data.py

Add separate well design rules.

2020-01-23 19:43:41 +00:00

precharge_array.py

write_driver/sense_amp/precharge arrays: Allow y axis mirroring

2020-01-28 15:51:39 +01:00

replica_bitcell_array.py

s8 gdsless netlist only working up to dff array

2020-02-09 21:37:09 -08:00

replica_column.py

Bitcell arrays: Allow mirroring on the y axis

2020-01-28 15:51:21 +01:00

sense_amp_array.py

Merge remote-tracking branch 'bkoppelmann/bit-sym' into dev

2020-01-29 11:24:09 -08:00

sense_amp.py

s8 gdsless netlist only working up to dff array

2020-02-09 21:37:09 -08:00

single_level_column_mux_array.py

column_mux: Allow y axis mirroring

2020-01-28 15:51:39 +01:00

tri_gate_array.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

tri_gate.py

Made all cin function relate to farads and all input_load relate to relative units.

2019-08-08 01:57:04 -07:00

wordline_driver.py

Pgates are 8 M1 high by default. Port data is bitcell height.

2020-01-30 03:34:04 +00:00

write_driver_array.py

Merge remote-tracking branch 'bkoppelmann/bit-sym' into dev

2020-01-29 11:24:09 -08:00

write_driver.py

s8 gdsless netlist only working up to dff array

2020-02-09 21:37:09 -08:00

write_mask_and_array.py

Move write mask vias to center to avoid data pins.

2019-12-20 11:48:27 -08:00