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OpenRAM
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OpenRAM/compiler
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Matt Guthaus 6b967c08dd Updated output messages in timing test comparisons. 
Added output to show which lines differ and what their line numbers are..
Added output to show relative difference of approximate compares.
Added output to include file names that mismatch.
 		2018-07-27 09:34:44 -07:00
..
base Remove print statement 2018-07-25 15:51:48 -07:00
characterizer Convert bitline index to integer in trim_spice 2018-07-26 14:29:44 -07:00
gdsMill Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
modules Limit sizes for dff_buf too. Add comments about restriction. 2018-07-27 08:17:50 -07:00
pgates Make pinvbuf have unique names for GDS compliance. 2018-07-26 11:40:40 -07:00
router Fix unit tests to be DRC clean. 2017-06-07 10:29:53 -07:00
tests Updated output messages in timing test comparisons. 2018-07-27 09:34:44 -07:00
verify Add temporary options to LVS to allow name merging 2018-07-18 15:10:29 -07:00
Makefile Add Makefile for parallel test execution. 2018-01-22 13:39:07 -08:00
debug.py Output debug warnings and errors to stderr. Clean up regress script a bit. 2018-07-11 09:51:28 -07:00
example_config_freepdk45.py Fix num words in example. 2018-02-23 12:17:43 -08:00
example_config_scn3me_subm.py Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library. 2018-02-12 11:22:47 -08:00
gen_stimulus.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
globals.py Only print LVS/DRC stats when it is enabled 2018-07-25 13:44:34 -07:00
openram.py Improve openram output. Fix save output function name. 2018-07-12 10:35:38 -07:00
options.py Fix options so it is in /tmp in RAM drive 2018-07-05 16:33:26 -07:00
sram.py Add verilog_write to sram wrapper for verilog unit test 2018-07-19 10:05:30 -07:00
sram_1bank.py Change DIN to DOUT in characterizer. Spacing dff flops down by m2 not m1 pitch. 2018-07-25 15:50:49 -07:00
sram_2bank.py Add LVS correspondence points to each bank type 2018-07-18 14:29:04 -07:00
sram_4bank.py Add LVS correspondence points to each bank type 2018-07-18 14:29:04 -07:00
sram_base.py Add LVS correspondence points to each bank type 2018-07-18 14:29:04 -07:00