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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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6ac5adaecad77d25d64f95de58c0acfe7ff9a5be
OpenRAM/compiler/router
T
History
Matt Guthaus 18d874a96a Fix error in iterative implementation of combine_classes
2018-11-14 10:05:04 -08:00
..
tests
Fix print check regression
2018-10-15 13:23:31 -07:00
direction.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
grid_cell.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
grid_path.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
grid_utils.py
Add expanded blockages for paths an enclosures to handle wide metal spacing rules.
2018-11-02 11:11:32 -07:00
grid.py
Supply router working except for off by one rail via error
2018-10-19 14:21:03 -07:00
pin_group.py
Expand blocked pins to neighbor grid cells.
2018-11-09 14:25:10 -08:00
router_tech.py
Pad the routing grid by a few tracks to add an extra rail
2018-11-02 17:35:35 -07:00
router.py
Fix error in iterative implementation of combine_classes
2018-11-14 10:05:04 -08:00
signal_grid.py
Rewrote pin enclosure code to better address off grid pins.
2018-10-10 15:15:58 -07:00
signal_router.py
Change non-preferred route costs.
2018-10-20 14:47:24 -07:00
supply_grid.py
Supply router working except:
2018-09-18 12:57:39 -07:00
supply_router.py
Reduce verbosity of level 1 debug.
2018-11-02 17:30:28 -07:00
vector3d.py
Add remove adjacent feature for wide metal spacing
2018-10-30 12:24:13 -07:00
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