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694ea5c20ea58d831068fde3c596548420f5f756
OpenRAM/compiler
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Aditi Sinha 694ea5c20e Characterization for extra rows
2020-02-20 17:31:58 +00:00
..
base
custom_cell_properties: Add bitcell pin name API
2020-02-12 15:37:51 +01:00
bitcells
bitcell: Remove hardcoded signal pins
2020-02-12 15:37:51 +01:00
characterizer
Merge branch 'dev' into bisr
2020-02-20 17:09:09 +00:00
datasheet
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
drc
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
example_configs
revert example scn4m to non netlist only
2020-02-09 23:52:11 -08:00
gdsMill
fixed purposes for gdsMill
2020-02-15 15:00:30 -08:00
modules
Characterization for extra rows
2020-02-20 17:31:58 +00:00
pgates
port_data: Each submodule now specifies their bl/br names
2020-02-12 15:00:50 +01:00
router
tech: Make power_grid configurable
2020-01-28 12:06:34 +01:00
sram
Merge branch 'dev' into bisr
2020-02-20 17:09:09 +00:00
tests
Characterization for extra rows
2020-02-20 17:31:58 +00:00
verify
Move DRC/LVS/PEX tools to tech file.
2019-11-29 12:01:33 -08:00
debug.py
Add layer-purpose GDS support. Various PEP8 fixes.
2019-11-14 18:17:20 +00:00
gen_stimulus.py
Characterization for extra rows
2020-02-20 17:01:52 +00:00
globals.py
Merge branch 'dev' into bisr
2020-02-20 17:09:09 +00:00
Makefile
Clean up Makefile for unit tests
2018-12-05 12:58:10 -08:00
openram.py
Characterization for extra rows
2020-02-20 17:01:52 +00:00
options.py
Blackbox option for DRC waivers
2019-11-29 15:50:32 -08:00
run_profile.sh
Convert pin map to a set for faster membership.
2019-04-01 15:45:44 -07:00
sram_factory.py
sram_factory: Add check for duplicate module name
2019-12-19 16:31:52 +01:00
view_profile.py
Remove some flake8 errors/warnings.
2019-10-02 23:26:02 +00:00