mirror of https://github.com/VLSIDA/OpenRAM.git
87b5a48f9e
use names provided by the tech file, which can be overriden by the technology. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> |
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|---|---|---|
| .. | ||
| bitcell.py | ||
| bitcell_1rw_1r.py | ||
| bitcell_1w_1r.py | ||
| bitcell_base.py | ||
| dummy_bitcell.py | ||
| dummy_bitcell_1rw_1r.py | ||
| dummy_bitcell_1w_1r.py | ||
| dummy_pbitcell.py | ||
| pbitcell.py | ||
| replica_bitcell.py | ||
| replica_bitcell_1rw_1r.py | ||
| replica_bitcell_1w_1r.py | ||
| replica_pbitcell.py | ||