mrg 07ef43eaf8 Convert design class data to static

2020-10-27 09:23:11 -07:00

..

bitcell_1rw_1r.py

Make conditional wl and bl for dummy rows/cols.

2020-10-15 13:56:37 -07:00

bitcell_1w_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

bitcell_base.py

update to new metal stack names

2020-07-31 05:27:19 -07:00

bitcell.py

Convert design class data to static

2020-10-27 09:23:11 -07:00

col_cap_bitcell_1rw_1r.py

Add option for removing subckt/instances of cells for row/col caps

2020-06-22 12:35:37 -07:00

dummy_bitcell_1rw_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

dummy_bitcell_1w_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

dummy_bitcell.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

dummy_pbitcell.py

Add bbox for special DRC rule boundary

2019-12-05 23:14:25 +00:00

pbitcell.py

update to new metal stack names

2020-07-31 05:27:19 -07:00

replica_bitcell_1rw_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

replica_bitcell_1w_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

replica_bitcell.py

Remove split_wl

2020-10-12 17:27:20 -07:00

replica_pbitcell.py

Add bbox for special DRC rule boundary

2019-12-05 23:14:25 +00:00

row_cap_bitcell_1rw_1r.py

Add option for removing subckt/instances of cells for row/col caps

2020-06-22 12:35:37 -07:00