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base
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Added custom 1rw+1r bitcell. Testing are currently failing.
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2018-10-22 17:02:21 -07:00 |
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characterizer
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Cleaned up indexing in variable that records cycle times.
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2018-10-10 00:02:03 -07:00 |
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gdsMill
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Added custom 1rw+1r bitcell. Testing are currently failing.
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2018-10-22 17:02:21 -07:00 |
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modules
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Added custom 1rw+1r bitcell. Testing are currently failing.
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2018-10-22 17:02:21 -07:00 |
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pgates
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Replacing replica_pbitcell module with a more effiecient verision. replica_pbitcell is now a wrapper for pbitcell in replica_bitcell mode.
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2018-09-13 16:53:24 -07:00 |
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router
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Remove banks from test configs
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2018-09-24 11:41:51 -07:00 |
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tests
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Added custom 1rw+1r bitcell. Testing are currently failing.
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2018-10-22 17:02:21 -07:00 |
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verify
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Put worst case test under the hierarchy of a delay test. Added option for pex option to worst case test.
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2018-10-09 00:36:14 -07:00 |
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Makefile
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Add Makefile for parallel test execution.
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2018-01-22 13:39:07 -08:00 |
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debug.py
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Output debug warnings and errors to stderr. Clean up regress script a bit.
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2018-07-11 09:51:28 -07:00 |
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example_config_freepdk45.py
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Altered web to only be generated for rw ports.
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2018-10-04 15:08:12 -07:00 |
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example_config_scn4m_subm.py
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Added custom 1rw+1r bitcell. Testing are currently failing.
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2018-10-22 17:02:21 -07:00 |
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gen_stimulus.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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globals.py
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Added class and test for testing the delay of several bitcells.
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2018-10-08 15:50:52 -07:00 |
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openram.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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options.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
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2018-09-27 02:02:24 -07:00 |
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sram.py
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Put worst case test under the hierarchy of a delay test. Added option for pex option to worst case test.
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2018-10-09 00:36:14 -07:00 |
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sram_1bank.py
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Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port.
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2018-09-26 19:10:24 -07:00 |
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sram_2bank.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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sram_4bank.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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sram_base.py
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Removing we_b signal from write ports since it is redundant.
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2018-10-04 09:31:04 -07:00 |
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sram_config.py
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Added custom 1rw+1r bitcell. Testing are currently failing.
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2018-10-22 17:02:21 -07:00 |
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