Matt Guthaus 4ebb8a26c4 Disable debug statements.

2018-11-13 17:43:08 -08:00

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base

Fix error when DRC is disabled so it doesn't initialize.

2018-11-13 17:41:32 -08:00

bitcells

Merge branch 'dev' into multiport_layout

2018-11-08 18:00:28 -08:00

characterizer

Fixed small bugs with new port index stuff and layout.

2018-11-08 17:40:22 -08:00

datasheet

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drc

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gdsMill

Allow multiple must-connect pins with the same label.

2018-11-07 13:05:13 -08:00

modules

Only check number of ports when doing layout.

2018-11-13 16:42:25 -08:00

pgates

Adjust ptx positions in precharge to be under the bl rail

2018-11-09 10:26:15 -08:00

router

Disable debug statements.

2018-11-13 17:43:08 -08:00

tests

Add multiport bank test

2018-11-13 16:06:21 -08:00

verify

Remove redundant DRC run in magic.

2018-11-05 13:30:42 -08:00

debug.py

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example_config_freepdk45.py

Remove options from example config files

2018-11-05 12:47:47 -08:00

example_config_scn4m_subm.py

Add magic/netgen to example config

2018-11-07 13:54:00 -08:00

gen_stimulus.py

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globals.py

Add new option to enable inline checks at each level of hierarchy. Default is off.

2018-11-13 16:51:19 -08:00

Makefile

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openram.py

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options.py

Add new option to enable inline checks at each level of hierarchy. Default is off.

2018-11-13 16:51:19 -08:00

sram_1bank.py

Initial two port bank in SCMOS

2018-11-13 16:05:22 -08:00

sram_2bank.py

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sram_4bank.py

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sram_base.py

Initial two port bank in SCMOS

2018-11-13 16:05:22 -08:00

sram_config.py

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sram.py

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