OpenRAM/compiler
mrg 4b06ab9eaf Move port 2 column address bus down.
PEP 8 cleanup.
2020-02-06 19:46:10 +00:00
..
base Add general well_extend_active DRC in design class. 2020-02-05 18:22:22 +00:00
bitcells Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
characterizer Check nominal_corner_only in new corner creation routine 2019-11-29 14:47:02 -08:00
datasheet Convert capital names to lower case for consistency 2019-08-21 13:45:34 -07:00
drc Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
example_configs Remove old drc/lvs override name 2019-12-16 10:05:52 -08:00
gdsMill Merge remote-tracking branch 'bkoppelmann/master' into dev 2019-12-11 08:46:52 -08:00
modules Nwell fixes in pgates. 2020-02-06 16:20:09 +00:00
pgates Move port 2 column address bus down. 2020-02-06 19:46:10 +00:00
router tech: Make power_grid configurable 2020-01-28 12:06:34 +01:00
sram Move port 2 column address bus down. 2020-02-06 19:46:10 +00:00
tests Add nwell/pwell tap test 2020-02-03 18:41:06 +00:00
verify Move DRC/LVS/PEX tools to tech file. 2019-11-29 12:01:33 -08:00
Makefile Clean up Makefile for unit tests 2018-12-05 12:58:10 -08:00
debug.py Add layer-purpose GDS support. Various PEP8 fixes. 2019-11-14 18:17:20 +00:00
gen_stimulus.py Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00
globals.py sram_factory: Give proper priority to overrides 2019-12-19 15:58:00 +01:00
openram.py Only setup bitcell when running top-level OpenRAM 2019-11-26 13:54:37 -08:00
options.py Blackbox option for DRC waivers 2019-11-29 15:50:32 -08:00
run_profile.sh Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
sram_factory.py sram_factory: Add check for duplicate module name 2019-12-19 16:31:52 +01:00
view_profile.py Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00