Matt Guthaus 90d1fa7c43 Bitcell supply routing fixes. ... Flatten and simplify 1rw 1r bitcell. Move bitcell vias to M3 if rotation is limited. Simplify replica bitcell vdd routing.		2018-11-30 12:32:13 -08:00
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bank.py	Fixed syntax error referring to column mux	2018-11-29 13:29:16 -08:00
bank_select.py	…
bitcell_array.py	Bitcell supply routing fixes.	2018-11-30 12:32:13 -08:00
control_logic.py	Remove used gated_clk instead of cs for read-only control logic.	2018-11-29 16:28:37 -08:00
delay_chain.py	…
dff.py	…
dff_array.py	Remove extra X in instance names	2018-11-27 12:02:53 -08:00
dff_buf.py	Modify dff_buf to stagger Q and Qb outputs.	2018-11-28 10:43:11 -08:00
dff_buf_array.py	Remove extra X in instance names	2018-11-27 12:02:53 -08:00
dff_inv.py	…
hierarchical_decoder.py	Make column decoder same height as control to control and supply overlaps	2018-11-28 16:59:58 -08:00
hierarchical_predecode.py	Fix col address dff spacing from bank.	2018-11-29 09:54:29 -08:00
hierarchical_predecode2x4.py	Make column decoder same height as control to control and supply overlaps	2018-11-28 16:59:58 -08:00
hierarchical_predecode3x8.py	Make column decoder same height as control to control and supply overlaps	2018-11-28 16:59:58 -08:00
multibank.py	…
precharge_array.py	Fix SRAM level control routing errors.	2018-11-28 15:30:52 -08:00
replica_bitline.py	Bitcell supply routing fixes.	2018-11-30 12:32:13 -08:00
sense_amp.py	…
sense_amp_array.py	…
single_level_column_mux_array.py	…
tri_gate.py	…
tri_gate_array.py	…
wordline_driver.py	Remove inverter in wordline driver	2018-11-26 16:41:31 -08:00
write_driver.py	…
write_driver_array.py	Remove extra X in instance names	2018-11-27 12:02:53 -08:00