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characterizer
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Fix broken print statements
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2018-02-07 17:39:42 -08:00 |
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gdsMill
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router
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tests
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Update replica bitline test for new parameters. Add small test and a larger test.
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2018-02-07 15:15:19 -08:00 |
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verify
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Add area/perimeter of source/drain to transistor netlist. Gets rid of some spice warnings, gives better non-annotated measurements.
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2018-02-05 16:02:57 -08:00 |
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Makefile
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Add Makefile for parallel test execution.
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2018-01-22 13:39:07 -08:00 |
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bank.py
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Ensure wells are spaced in the bank select and column decoder
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2018-02-02 15:26:15 -08:00 |
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bitcell.py
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bitcell_array.py
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Fix pin names to lower case. Fix write driver DRC errors and LVS error.
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2018-01-31 17:37:16 -08:00 |
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contact.py
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control_logic.py
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Make delay chain length and bitcell load parameters to enable tuning. Rename the parameters to be more descriptive.
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2018-02-07 14:54:59 -08:00 |
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debug.py
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Clean up messages.
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2018-01-31 11:54:20 -08:00 |
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delay_chain.py
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Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.
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2018-01-19 16:38:19 -08:00 |
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design.py
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Disable virtual connects at top level LVS with Calibre.
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2018-02-05 14:52:51 -08:00 |
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example_config_freepdk45.py
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Fix bug in trim netlist. Add info comments to spice netlist and trimmed netlist. Increase verbosity for simulations.
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2018-02-02 19:33:07 -08:00 |
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example_config_scn3me_subm.py
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Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.
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2018-01-19 16:38:19 -08:00 |
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geometry.py
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globals.py
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Remove version from OpenRAM. We will go bit git hashes.
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2018-02-06 10:56:26 -08:00 |
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hierarchical_decoder.py
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Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.
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2018-01-19 16:38:19 -08:00 |
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hierarchical_predecode.py
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Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder.
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2018-02-02 14:08:56 -08:00 |
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hierarchical_predecode2x4.py
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Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder.
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2018-02-02 14:08:56 -08:00 |
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hierarchical_predecode3x8.py
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Fix input discrepencies in pre3x8
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2018-01-29 15:25:41 -08:00 |
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hierarchy_layout.py
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Simplify via offsets in replica bitline. Route clk_bar in control over supply rail until we get channel router working.
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2018-02-05 10:22:38 -08:00 |
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hierarchy_spice.py
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Remove level of indirection to ptx devices to allow LVS symmetries.
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2018-01-29 15:25:15 -08:00 |
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lef.py
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ms_flop.py
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ms_flop_array.py
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Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.
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2018-01-19 16:38:19 -08:00 |
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openram.py
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Add Makefile for parallel test execution.
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2018-01-22 13:39:07 -08:00 |
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options.py
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Add -d option to not delete temp directory on successful runs.
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2018-02-01 11:53:02 -08:00 |
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path.py
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pgate.py
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Fix 6T and replica cell contact spacing issues with Magic DRC.
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2018-01-26 12:39:00 -08:00 |
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pin_layout.py
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pinv.py
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Fix 6T and replica cell contact spacing issues with Magic DRC.
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2018-01-26 12:39:00 -08:00 |
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pnand2.py
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Fix wrong pin order on pnand2 LVS problem.
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2018-01-29 15:31:14 -08:00 |
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pnand3.py
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Fix wrong pin order on pnand2 LVS problem.
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2018-01-29 15:31:14 -08:00 |
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pnor2.py
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Fix 6T and replica cell contact spacing issues with Magic DRC.
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2018-01-26 12:39:00 -08:00 |
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precharge.py
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Fix precharge nwell contact spacing DRC violatin.
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2018-01-26 13:53:45 -08:00 |
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precharge_array.py
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ptx.py
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Add area/perimeter of source/drain to transistor netlist. Gets rid of some spice warnings, gives better non-annotated measurements.
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2018-02-05 16:02:57 -08:00 |
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regress.sh
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replica_bitcell.py
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replica_bitline.py
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Make delay chain length and bitcell load parameters to enable tuning. Rename the parameters to be more descriptive.
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2018-02-07 14:54:59 -08:00 |
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route.py
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Fix gnd connection in control logic.
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2018-02-02 13:04:38 -08:00 |
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sense_amp.py
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sense_amp_array.py
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Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.
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2018-01-19 16:38:19 -08:00 |
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single_level_column_mux.py
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Clean up column mux by moving pins to own function. Adjust spacing between column mux and bitcell to prevent DRCs. Fix up find lowest/highest functions when no objects or instances in a module.
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2018-02-02 15:17:21 -08:00 |
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single_level_column_mux_array.py
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Clean up column mux by moving pins to own function. Adjust spacing between column mux and bitcell to prevent DRCs. Fix up find lowest/highest functions when no objects or instances in a module.
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2018-02-02 15:17:21 -08:00 |
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sram.py
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Disable virtual connects at top level LVS with Calibre.
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2018-02-05 14:52:51 -08:00 |
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tri_gate.py
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tri_gate_array.py
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Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.
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2018-01-19 16:38:19 -08:00 |
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utils.py
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vector.py
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verilog.py
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wire.py
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Fix gnd connection in control logic.
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2018-02-02 13:04:38 -08:00 |
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wordline_driver.py
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Fix nand input ordering to correct netgen LVS error of wordline driver.
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2018-01-29 15:36:37 -08:00 |
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write_driver.py
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Fix pin names to lower case. Fix write driver DRC errors and LVS error.
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2018-01-31 17:37:16 -08:00 |
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write_driver_array.py
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Fix pin names to lower case. Fix write driver DRC errors and LVS error.
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2018-01-31 17:37:16 -08:00 |
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