Matt Guthaus 19c0e1638b Merge remote-tracking branch 'origin/multiport' into multiport

2018-09-04 10:47:55 -07:00

..

bank_select.py

Move place function to instance class rather than hierarchy.

2018-08-27 17:25:39 -07:00

bank.py

Merge remote-tracking branch 'origin/multiport' into multiport

2018-09-04 10:47:55 -07:00

bitcell_array.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

bitcell.py

Changing function names in bitcell and pbitcell to better reflect what values they're returning. Editting function calls in bitcell_array and bank accordingly.

2018-08-26 14:37:17 -07:00

control_logic.py

Move place function to instance class rather than hierarchy.

2018-08-27 17:25:39 -07:00

delay_chain.py

Unrotate vias in delay chain

2018-08-29 17:21:53 -07:00

dff_array.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

dff_buf_array.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

dff_buf.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

dff_inv_array.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

dff_inv.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

dff.py

Add dff_buf for buffered flop arrays.

2018-03-04 16:13:10 -08:00

hierarchical_decoder.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

hierarchical_predecode2x4.py

Converted all modules to not run create_layout when netlist_only

2018-08-27 16:42:48 -07:00

hierarchical_predecode3x8.py

Converted all modules to not run create_layout when netlist_only

2018-08-27 16:42:48 -07:00

hierarchical_predecode.py

Move place function to instance class rather than hierarchy.

2018-08-27 17:25:39 -07:00

ms_flop_array.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

ms_flop.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

multibank.py

Initial refactor of signal and supply router classes.

2018-08-29 15:34:45 -07:00

precharge_array.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

replica_bitcell.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00

replica_bitline.py

Rewrite blockage routines in router. Clean up GdsMill code.

2018-08-29 15:34:45 -07:00

sense_amp_array.py

Altering sense amp array and write driver array so spacing between amps/drivers accomodates multiport. Also altering sense amp array and write driver array tests to include multiport cases.

2018-08-31 23:28:06 -07:00

sense_amp.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

single_level_column_mux_array.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

tri_gate_array.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

tri_gate.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

wordline_driver.py

Altering wordline driver to size for any bitcell. Editting multi-port test cases for sense amp array, write driver array, and wordline driver to least number of ports as a better test of spacing betwwen amps/drivers

2018-09-03 17:31:12 -07:00

write_driver_array.py

Altering sense amp array and write driver array so spacing between amps/drivers accomodates multiport. Also altering sense amp array and write driver array tests to include multiport cases.

2018-08-31 23:28:06 -07:00

write_driver.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00