Hunter Nichols edac60d2a8 Merged with dev and fixed conflicts.

2019-04-03 16:45:01 -07:00

..

bank_select.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

bank.py

Added analyical model test which compares measured delay to model delay.

2019-04-03 16:26:20 -07:00

bitcell_array.py

Added analyical model test which compares measured delay to model delay.

2019-04-03 16:26:20 -07:00

control_logic.py

Merged with dev and fixed conflicts.

2019-04-03 16:45:01 -07:00

delay_chain.py

Added some comments to the spice files.

2019-01-25 15:00:00 -08:00

dff_array.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

dff_buf_array.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

dff_buf.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

dff_inv_array.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

dff_inv.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

dff.py

Added corner information for analytical power estimation.

2019-03-04 19:27:53 -08:00

hierarchical_decoder.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

hierarchical_predecode2x4.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

hierarchical_predecode3x8.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

hierarchical_predecode.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

multibank.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

precharge_array.py

Added some comments to the spice files.

2019-01-25 15:00:00 -08:00

replica_bitline.py

Change pbuf/pinv to pdriver in control logic.

2019-01-23 12:03:52 -08:00

sense_amp_array.py

Added analyical model test which compares measured delay to model delay.

2019-04-03 16:26:20 -07:00

sense_amp.py

Added updated analytical characterization with combined models

2019-04-02 01:09:31 -07:00

single_level_column_mux_array.py

Added analyical model test which compares measured delay to model delay.

2019-04-03 16:26:20 -07:00

tri_gate_array.py

Update unit tests to all use the sram_factory

2019-03-06 14:12:24 -08:00

tri_gate.py

Added corner information for analytical power estimation.

2019-03-04 19:27:53 -08:00

wordline_driver.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

write_driver_array.py

Added some comments to the spice files.

2019-01-25 15:00:00 -08:00

write_driver.py

Change pbuf/pinv to pdriver in control logic.

2019-01-23 12:03:52 -08:00