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luke
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OpenRAM
mirror of
https://github.com/VLSIDA/OpenRAM.git
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0e7301fff8
OpenRAM
/
compiler
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modules
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Matt Guthaus
33a7683473
Remove used gated_clk instead of cs for read-only control logic.
2018-11-29 16:28:37 -08:00
..
bank.py
…
bank_select.py
…
bitcell_array.py
…
control_logic.py
Remove used gated_clk instead of cs for read-only control logic.
2018-11-29 16:28:37 -08:00
delay_chain.py
…
dff.py
…
dff_array.py
…
dff_buf.py
…
dff_buf_array.py
…
dff_inv.py
…
hierarchical_decoder.py
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hierarchical_predecode.py
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hierarchical_predecode2x4.py
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hierarchical_predecode3x8.py
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multibank.py
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precharge_array.py
…
replica_bitline.py
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sense_amp.py
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sense_amp_array.py
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single_level_column_mux_array.py
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tri_gate.py
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tri_gate_array.py
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wordline_driver.py
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write_driver.py
…
write_driver_array.py
…