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base
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Add create_bus and connect_bus api
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2018-07-17 14:23:29 -07:00 |
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characterizer
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Use sram rather than new meta-sram class in the characterizer for delay
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2018-07-18 10:39:29 -07:00 |
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gdsMill
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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modules
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Space hier decoder input connections along rails to avoid conflicts
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2018-07-18 10:21:58 -07:00 |
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pgates
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Remove uniqe pbitcell id since it isn't needed. Convert dos EOL to unix EOL characters. Convert python2.7 to python3 in pbitcell.
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2018-06-29 11:49:02 -07:00 |
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router
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Fix unit tests to be DRC clean.
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2017-06-07 10:29:53 -07:00 |
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tests
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Fix syntax error in delay test to use new sram wrapper module
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2018-07-18 10:33:18 -07:00 |
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verify
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Add DRC/LVS/PEX statistics in verbose=1 mode
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2018-07-11 11:59:24 -07:00 |
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Makefile
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Add Makefile for parallel test execution.
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2018-01-22 13:39:07 -08:00 |
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debug.py
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Output debug warnings and errors to stderr. Clean up regress script a bit.
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2018-07-11 09:51:28 -07:00 |
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example_config_freepdk45.py
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Fix num words in example.
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2018-02-23 12:17:43 -08:00 |
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example_config_scn3me_subm.py
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Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library.
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2018-02-12 11:22:47 -08:00 |
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gen_stimulus.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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globals.py
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Fix order of checkpointing so that it is done after characterizer and verify have found their executables.
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2018-07-11 12:12:03 -07:00 |
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openram.py
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Improve openram output. Fix save output function name.
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2018-07-12 10:35:38 -07:00 |
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options.py
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Fix options so it is in /tmp in RAM drive
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2018-07-05 16:33:26 -07:00 |
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sram.py
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Getting single bank to work reliably. Removed tri_gate from bank
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2018-07-13 14:45:46 -07:00 |
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sram_1bank.py
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Single bank working except for channel routing error in 4-way case.
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2018-07-17 14:40:04 -07:00 |
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sram_2bank.py
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Reference local sram instance in sram.py.
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2018-07-13 09:30:14 -07:00 |
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sram_4bank.py
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Reference local sram instance in sram.py.
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2018-07-13 09:30:14 -07:00 |
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sram_base.py
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Must connect clock at top level for now
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2018-07-17 14:24:07 -07:00 |
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