mirror of https://github.com/VLSIDA/OpenRAM.git
195 lines
7.9 KiB
Python
195 lines
7.9 KiB
Python
import sys
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from tech import drc, spice
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import debug
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from math import log,sqrt,ceil
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import datetime
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import getpass
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from vector import vector
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from globals import OPTS, print_time
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from sram_base import sram_base
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from bank import bank
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from dff_buf_array import dff_buf_array
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from dff_array import dff_array
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class sram_1bank(sram_base):
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"""
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Procedures specific to a one bank SRAM.
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"""
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def __init__(self, word_size, num_words, name):
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sram_base.__init__(self, word_size, num_words, 1, name)
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def add_modules(self):
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"""
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This adds the moduels for a single bank SRAM with control
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logic.
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"""
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# No orientation or offset
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self.bank_inst = self.add_bank(0, [0, 0], 1, 1)
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control_pos = vector(-self.control_logic.width - self.m3_pitch,
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self.bank.bank_center.y - self.control_logic.control_logic_center.y)
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self.add_control_logic(position=control_pos)
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# Leave room for the control routes to the left of the flops
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row_addr_pos = vector(self.control_logic_inst.rx() - self.row_addr_dff.width,
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control_pos.y + self.control_logic.height + self.m1_pitch)
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self.add_row_addr_dff(row_addr_pos)
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data_gap = -self.m2_pitch*(self.word_size+1)
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# Add the column address below the bank under the control
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# Keep it aligned with the data flops
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if self.col_addr_dff:
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col_addr_pos = vector(self.bank.bank_center.x - self.col_addr_dff.width - self.bank.central_bus_width,
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data_gap - self.col_addr_dff.height)
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self.add_col_addr_dff(col_addr_pos)
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# Add the data flops below the bank
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# This relies on the center point of the bank:
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# decoder in upper left, bank in upper right, sensing in lower right.
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# These flops go below the sensing and leave a gap to channel route to the
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# sense amps.
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data_pos = vector(self.bank.bank_center.x,
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data_gap - self.data_dff.height)
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self.add_data_dff(data_pos)
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# two supply rails are already included in the bank, so just 2 here.
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self.width = self.bank.width + self.control_logic.width + 2*self.supply_rail_pitch
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self.height = self.bank.height
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def add_layout_pins(self):
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"""
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Add the top-level pins for a single bank SRAM with control.
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"""
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# Connect the control pins as inputs
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for n in self.control_logic_inputs + ["clk"]:
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self.copy_layout_pin(self.control_logic_inst, n)
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for i in range(self.word_size):
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self.copy_layout_pin(self.bank_inst, "DOUT[{}]".format(i))
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# Lower address bits
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for i in range(self.col_addr_size):
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self.copy_layout_pin(self.col_addr_dff_inst, "din[{}]".format(i),"ADDR[{}]".format(i))
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# Upper address bits
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for i in range(self.row_addr_size):
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self.copy_layout_pin(self.row_addr_dff_inst, "din[{}]".format(i),"ADDR[{}]".format(i+self.col_addr_size))
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for i in range(self.word_size):
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self.copy_layout_pin(self.data_dff_inst, "din[{}]".format(i),"DIN[{}]".format(i))
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def route(self):
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""" Route a single bank SRAM """
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self.add_layout_pins()
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self.route_vdd_gnd()
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self.route_clk()
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self.route_control_logic()
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self.route_row_addr_dff()
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if self.col_addr_dff:
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self.route_col_addr_dff()
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self.route_data_dff()
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def route_clk(self):
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""" Route the clock network """
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debug.warning("Clock is top-level must connect.")
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# For now, just have four clock pins for the address (x2), data, and control
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if self.col_addr_dff:
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self.copy_layout_pin(self.col_addr_dff_inst, "clk")
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self.copy_layout_pin(self.row_addr_dff_inst, "clk")
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self.copy_layout_pin(self.data_dff_inst, "clk")
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self.copy_layout_pin(self.control_logic_inst, "clk")
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def route_vdd_gnd(self):
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""" Propagate all vdd/gnd pins up to this level for all modules """
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# These are the instances that every bank has
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top_instances = [self.bank_inst,
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self.row_addr_dff_inst,
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self.data_dff_inst,
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self.control_logic_inst]
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if self.col_addr_dff:
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top_instances.append(self.col_addr_dff_inst)
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for inst in top_instances:
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self.copy_layout_pin(inst, "vdd")
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self.copy_layout_pin(inst, "gnd")
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def route_control_logic(self):
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""" Route the outputs from the control logic module """
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for n in self.control_logic_outputs:
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src_pin = self.control_logic_inst.get_pin(n)
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dest_pin = self.bank_inst.get_pin(n)
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self.connect_rail_from_left_m2m3(src_pin, dest_pin)
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=src_pin.rc(),
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rotate=90)
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def route_row_addr_dff(self):
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""" Connect the output of the row flops to the bank pins """
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for i in range(self.row_addr_size):
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flop_name = "dout[{}]".format(i)
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bank_name = "A[{}]".format(i+self.col_addr_size)
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flop_pin = self.row_addr_dff_inst.get_pin(flop_name)
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bank_pin = self.bank_inst.get_pin(bank_name)
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flop_pos = flop_pin.center()
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bank_pos = bank_pin.center()
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mid_pos = vector(bank_pos.x,flop_pos.y)
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self.add_wire(("metal3","via2","metal2"),[flop_pos, mid_pos,bank_pos])
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self.add_via_center(layers=("metal2","via2","metal3"),
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offset=flop_pos,
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rotate=90)
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def route_col_addr_dff(self):
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""" Connect the output of the row flops to the bank pins """
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bus_names = ["A[{}]".format(x) for x in range(self.col_addr_size)]
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col_addr_bus_offsets = self.create_horizontal_bus(layer="metal1",
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pitch=self.m1_pitch,
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offset=self.col_addr_dff_inst.ul() + vector(0, self.m1_pitch),
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names=bus_names,
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length=self.col_addr_dff_inst.width)
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dff_names = ["dout[{}]".format(x) for x in range(self.col_addr_size)]
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data_dff_map = zip(dff_names, bus_names)
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self.connect_horizontal_bus(data_dff_map, self.col_addr_dff_inst, col_addr_bus_offsets)
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bank_names = ["A[{}]".format(x) for x in range(self.col_addr_size)]
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data_bank_map = zip(bank_names, bus_names)
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self.connect_horizontal_bus(data_bank_map, self.bank_inst, col_addr_bus_offsets)
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def route_data_dff(self):
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""" Connect the output of the data flops to the write driver """
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# Create a horizontal bus
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bus_names = ["data[{}]".format(x) for x in range(self.word_size)]
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data_bus_offsets = self.create_horizontal_bus(layer="metal1",
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pitch=self.m1_pitch,
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offset=self.data_dff_inst.ul() + vector(0, self.m1_pitch),
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names=bus_names,
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length=self.data_dff_inst.width)
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dff_names = ["dout[{}]".format(x) for x in range(self.word_size)]
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data_dff_map = zip(dff_names, bus_names)
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self.connect_horizontal_bus(data_dff_map, self.data_dff_inst, data_bus_offsets)
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bank_names = ["BANK_DIN[{}]".format(x) for x in range(self.word_size)]
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data_bank_map = zip(bank_names, bus_names)
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self.connect_horizontal_bus(data_bank_map, self.bank_inst, data_bus_offsets)
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