Matt Guthaus 0665d51249 Must connect clock at top level for now

2018-07-17 14:24:07 -07:00

..

base

Add create_bus and connect_bus api

2018-07-17 14:23:29 -07:00

characterizer

Split DATA into DIN and DOUT in characterizer

2018-07-11 14:19:09 -07:00

gdsMill

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

modules

Convert predecodes to use create_bus api

2018-07-17 14:23:06 -07:00

pgates

Remove uniqe pbitcell id since it isn't needed. Convert dos EOL to unix EOL characters. Convert python2.7 to python3 in pbitcell.

2018-06-29 11:49:02 -07:00

router

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tests

Getting single bank to work reliably. Removed tri_gate from bank

2018-07-13 14:45:46 -07:00

verify

Add DRC/LVS/PEX statistics in verbose=1 mode

2018-07-11 11:59:24 -07:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

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example_config_scn3me_subm.py

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gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

Fix order of checkpointing so that it is done after characterizer and verify have found their executables.

2018-07-11 12:12:03 -07:00

Makefile

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openram.py

Improve openram output. Fix save output function name.

2018-07-12 10:35:38 -07:00

options.py

Fix options so it is in /tmp in RAM drive

2018-07-05 16:33:26 -07:00

sram_1bank.py

Convert bank to use create_bus routines.

2018-07-16 14:13:41 -07:00

sram_2bank.py

Reference local sram instance in sram.py.

2018-07-13 09:30:14 -07:00

sram_4bank.py

Reference local sram instance in sram.py.

2018-07-13 09:30:14 -07:00

sram_base.py

Must connect clock at top level for now

2018-07-17 14:24:07 -07:00

sram.py

Getting single bank to work reliably. Removed tri_gate from bank

2018-07-13 14:45:46 -07:00