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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-07 11:21:14 +02:00
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00347987871174c7d4f1231263b6c7e9d522bfa0
OpenRAM/technology/sky130/custom
T
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Jesse Cirimelli-Low 0034798787 both rbl replica array working
2023-09-11 11:23:39 -07:00
..
__init__.py
Use packages for imports.
2022-07-13 15:55:57 -07:00
sky130_bitcell_array.py
work on capped rba
2023-08-25 16:39:32 -07:00
sky130_bitcell_base_array.py
rba done w/o wordline
2023-08-24 02:55:45 -07:00
sky130_bitcell.py
work on capped rba
2023-08-25 16:39:32 -07:00
sky130_capped_replica_bitcell_array.py
various refactor changes
2023-08-28 12:31:55 -07:00
sky130_col_cap_array.py
single port sky130 crba passing lvs
2023-08-30 20:59:02 -07:00
sky130_col_cap.py
Update copyright year
2023-01-28 22:56:27 -08:00
sky130_corner.py
placement working for sp capped rba, need fix rowcap patterns
2023-08-26 18:54:07 -07:00
sky130_dummy_array.py
both rbl replica array working
2023-09-11 11:23:39 -07:00
sky130_dummy_bitcell.py
Update copyright year
2023-01-28 22:56:27 -08:00
sky130_internal.py
Update copyright year
2023-01-28 22:56:27 -08:00
sky130_replica_bitcell_array.py
work on capped rba
2023-08-25 16:39:32 -07:00
sky130_replica_bitcell.py
Update copyright year
2023-01-28 22:56:27 -08:00
sky130_replica_column.py
rba done w/o wordline
2023-08-24 02:55:45 -07:00
sky130_row_cap_array.py
various refactor changes
2023-08-28 12:31:55 -07:00
sky130_row_cap.py
Update copyright year
2023-01-28 22:56:27 -08:00
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