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4,392 Commits 5 Branches 63 Tags
v1.2.19
Commit Graph
7 Commits
Author SHA1 Message Date
Gary Mejia 9a36cce7ae Fixed formatting on all files 2023-06-14 12:28:36 -07:00
Gary Mejia 692acd2066 Verilog ROM model created for testing 2023-06-12 15:35:54 -07:00
Sage Walker b2bcbddd01 ROM binary file support 2023-04-03 16:04:12 -07:00
mrg 56e14113aa Change rom_base_bank name and top pin names 2023-03-30 11:30:50 -07:00
Jacob Walker eec0f02bb8 skip test file 2023-03-30 11:30:50 -07:00
Jacob Walker b50ec272da updated top level rom unit tests 2023-03-30 11:30:50 -07:00
Jacob Walker 41f0b9a412 rom compiler top level 2023-03-30 11:30:50 -07:00