Matt Guthaus
410115e830
Modify dff_buf to stagger Q and Qb outputs.
2018-11-28 10:43:11 -08:00
Matt Guthaus
ea6abfadb7
Stagger outputs of dff_buf
2018-11-28 09:48:16 -08:00
Matt Guthaus
5e0eb609da
Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.
2018-11-16 11:48:41 -08:00
Matt Guthaus
aa779a7f82
Initial two port bank in SCMOS
2018-11-13 16:05:22 -08:00
Matt Guthaus
e17c69be3e
Clean up new code for add_modules, add_pins and netlist/layouts.
2018-08-28 10:24:09 -07:00
Matt Guthaus
01cbc71a2a
Limit sizes for dff_buf too. Add comments about restriction.
2018-07-27 08:17:50 -07:00
Matt Guthaus
f34c4eb7dc
Convert entire OpenRAM to use python3. Works with Python 3.6.
...
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
2018-05-14 16:15:45 -07:00
Matt Guthaus
97c08bce95
Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.
...
Shift s_en buffers even with other cells.
2018-03-23 08:14:09 -07:00
Matt Guthaus
c020d74f26
Add dff_buf and dff_array modules.
2018-03-23 08:11:51 -07:00
Matt Guthaus
a2514878c1
Simplify dff array names of 1-dimension. Add ports on metal2.
2018-03-05 16:22:35 -08:00
Matt Guthaus
8d9b79dfd8
Add dff_buf for buffered flop arrays.
2018-03-04 16:13:10 -08:00