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OpenRAM
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217 Commits

Author SHA1 Message Date
Michael Timothy Grimes ecd4612167 altered bitcell, pbitcell, and bitcell array modules to accomodate additional bitline reference functions 2018-08-05 19:43:59 -07:00
Michael Timothy Grimes fb0de710ec Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-07-26 09:04:59 -07:00
Michael Timothy Grimes 27ab411146 fixed error I missed in pbitcell_array test 2018-07-26 09:02:52 -07:00
Matt Guthaus b88947ef5c Pass the sram design to lib instead of the sram wrapper 2018-07-18 11:51:42 -07:00
Matt Guthaus 1130062343 Fix syntax error in delay test to use new sram wrapper module 2018-07-18 10:33:18 -07:00
Matt Guthaus b8e3629923 Fix syntax error in unit test 2018-07-17 15:14:22 -07:00
Matt Guthaus 01655b1d54 Clean up tests. Enable 8-way tests. Some tests still have channel route conflicts. 2018-07-17 15:13:00 -07:00
Matt Guthaus f3ae29fe0b Getting single bank to work reliably. Removed tri_gate from bank 
for now. Will add it in multibank arrays only. Not needed for
separate DIN and DOUT ports.
 2018-07-13 14:45:46 -07:00
Matt Guthaus 834fbac8de Remove extra print statements. 
Add wrappers for file generation in sram wrapper class.
 2018-07-13 09:38:43 -07:00
Michael Timothy Grimes 2388ddbfb0 deleting code added in error to pbitcell_array_test during previous commit 2018-07-12 23:55:54 -07:00
Michael Timothy Grimes ba43b986ae merging changes with pbitcell_array test 2018-07-12 23:51:44 -07:00
Michael Timothy Grimes a64ca423c6 changing pbitcell_array test to include an important permutation of the design 2018-07-12 23:45:47 -07:00
Matt Guthaus c71ea51e2e Merge branch 'multiport_cleanup' of github.com:VLSIDA/PrivateRAM into multiport_cleanup 2018-07-11 14:27:41 -07:00
Matt Guthaus 22d40364ec Merge branch 'multiport_cleanup' of https://github.com/VLSIDA/PrivateRAM into multiport_cleanup 2018-07-11 14:27:06 -07:00
Matt Guthaus 33bb98894f Disable LEF test until supplies fixed. 2018-07-11 14:18:53 -07:00
Matt Guthaus 8be88d14a7 Disable banner output during gitlab runner 2018-07-11 14:18:36 -07:00
Matt Guthaus 8a530da2cc Remove extra conversion to list 2018-07-11 12:07:37 -07:00
Matt Guthaus 265b5d977a Fix option reload problems and checkpointing so that it works properly. 2018-07-11 12:00:15 -07:00
Matt Guthaus 58646ab8e6 Add DRC/LVS/PEX statistics in verbose=1 mode 2018-07-11 11:59:24 -07:00
Matt Guthaus f894ef47af Fix missing list conversion to run drc library tests. 2018-07-11 11:58:22 -07:00
Matt Guthaus b3732f4fcf Output debug warnings and errors to stderr. Clean up regress script a bit. 2018-07-11 09:51:28 -07:00
Matt Guthaus f82591dd6f Remove outdated README 2018-07-11 09:12:20 -07:00
Matt Guthaus c6503dd771 Modify unit tests to reset options during init_openram so 
that they don't use old parameters after a failure.
 2018-07-10 16:39:32 -07:00
Matt Guthaus 19c53cd50c Do not fail assertion in exception code. 2018-07-10 14:16:18 -07:00
Matt Guthaus 019512bc25 Fix python3 module reference in functional test 2018-07-09 16:07:53 -07:00
Matt Guthaus f234e43241 Reset new hierarchy_design instead of design for duplicate GDS name checker 2018-07-09 16:07:30 -07:00
Matt Guthaus bbc98097ac Add getpass include to unit test 30 2018-07-09 15:53:37 -07:00
Matt Guthaus 7bf271fd63 Skip pex and functional tests which are not working. 2018-07-09 15:52:07 -07:00
Matt Guthaus 5cf62e82cf Merge branch 'dev' into multiport_cleanup 2018-07-09 09:58:13 -07:00
Matt Guthaus a9a95ebf7c Fix pex test permissions 2018-07-09 09:11:14 -07:00
Matt Guthaus 5d32a426c4 Change test sram path so jobs can be simultaneously run. 2018-07-06 07:34:38 -07:00
Matt Guthaus 733be110a2 Add negation to return code so tests fail or pass properly. 2018-07-06 07:27:26 -07:00
Matt Guthaus 3260468477 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2018-07-05 16:27:49 -07:00
Matt Guthaus 077f3f20ec Add return code for regression test 2018-07-05 16:27:47 -07:00
Matt Guthaus 99fe3b87fe Remove temp file. Fixing indexing of sense amp outputs. 2018-06-29 15:22:58 -07:00
Matt Guthaus 6ac24dbf0c Fix module name for python3 2018-06-29 15:12:15 -07:00
Matt Guthaus 8d61ccbc6f Convert byte string to string. 2018-06-29 15:11:14 -07:00
Matt Guthaus 6cd1779f7b Rename pex test so that it ends with _test and will be run by regress.py. 2018-06-29 12:47:22 -07:00
Matt Guthaus 32099646cf Add back fix to revert bitcell from pbitcell. 2018-06-29 12:45:26 -07:00
Matt Guthaus a9849eff3a Merge in mtgrime's fix. 2018-06-29 12:44:26 -07:00
Michael Timothy Grimes 82eeb297dd Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-06-29 12:07:03 -07:00
Michael Timothy Grimes 721f935d66 changing pbitcell tests to revert OPTS.bitcell to bitcell after tests 2018-06-29 12:00:36 -07:00
Matt Guthaus ac7aa4537c Remove uniqe pbitcell id since it isn't needed. Convert dos EOL to unix EOL characters. Convert python2.7 to python3 in pbitcell. 2018-06-29 11:49:02 -07:00
Matt Guthaus fa17d5e7f3 Change permissions of tests to be executable so you don't have to type python each time. 2018-06-29 11:36:30 -07:00
Matt Guthaus 3becf92e7c Combine pbitcell tests into one unit test 2018-06-29 10:00:23 -07:00
Matt Guthaus df2dce2439 Fix module import names for python3. Rename parse function to something meaningful. 2018-06-29 09:45:07 -07:00
Michael Timothy Grimes d7a024b8fc adding another important port combination to unit tests 2018-06-03 19:36:48 -07:00
Michael Timothy Grimes e19a422696 simplfying calculations in pbitcell and changing pbitcell_array_test to check different port combinations 2018-05-31 17:39:51 -07:00
Michael Timothy Grimes 8f131ddb2f commiting changes from most recent pull from dev 2018-05-22 17:30:51 -07:00
Michael Timothy Grimes b5df0cc30a Merging branch with PrivateRAM dev 2018-05-18 15:15:31 -07:00