Eren Dogan
0a1de57cae
Update copyright year
2024-01-03 14:32:44 -08:00
Eren Dogan
e5fc25da6f
Update copyright year
2023-01-28 22:56:27 -08:00
Eren Dogan
96e57507bf
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
Eren Dogan
fccdc3c45b
Use library imports globally
2022-11-27 13:01:20 -08:00
mrg
d92c7a634d
Use packages for imports.
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Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
2022-07-13 15:55:57 -07:00
mrg
0c3ee643ab
Remove add_mod and add module whenever calling add_inst.
2021-11-22 11:33:27 -08:00
Matt Guthaus
30fc81a1f0
Update copyright year.
2021-01-22 11:23:28 -08:00
mrg
da721a677d
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
Hunter Nichols
73b2277daa
Removed dead code related to older characterization scheme
2020-08-27 17:30:58 -07:00
mrg
30976df48f
Change inheritance inits to use super
2020-08-06 11:33:26 -07:00
Matt Guthaus
ed28b4983b
Clean up and generalize layer rules.
...
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
2019-12-17 11:03:36 -08:00
Hunter Nichols
2ce7323838
Removed all unused analytical delay functions.
2019-08-06 17:09:25 -07:00
Matt Guthaus
6e044b776f
Merge branch 'pep8_cleanup' into dev
2019-06-14 08:47:10 -07:00
Matt Guthaus
a234b0af88
Fix space before comment
2019-06-14 08:43:41 -07:00
mrg
fc12ea24e9
Add boundary to every module and pgate for visual debug.
2019-06-03 15:27:37 -07:00
Matt Guthaus
0f03553689
Update copyright to correct years.
2019-05-06 06:50:15 -07:00
Matt Guthaus
3f9a987e51
Update copyright. Add header to all OpenRAM files.
2019-04-26 12:33:53 -07:00
Hunter Nichols
0e96648211
Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
Matt Guthaus
0c3baa5172
Added some comments to the spice files.
2019-01-25 15:00:00 -08:00
Matt Guthaus
a418431a42
First draft of sram_factory code
2019-01-16 16:15:38 -08:00
Hunter Nichols
e8f1c19af6
Merge branch 'dev' into multiport_characterization
2018-11-19 15:42:48 -08:00
Matt Guthaus
5e0eb609da
Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.
2018-11-16 11:48:41 -08:00
Hunter Nichols
b8061d3a4e
Added initial code for determining the logical effort delay of the wordline.
2018-11-08 23:54:18 -08:00
Matt Guthaus
e17c69be3e
Clean up new code for add_modules, add_pins and netlist/layouts.
2018-08-28 10:24:09 -07:00
Matt Guthaus
6401cbf2a6
Move place function to instance class rather than hierarchy.
2018-08-27 17:25:39 -07:00
Matt Guthaus
8664f7a0b8
Converted all modules to not run create_layout when netlist_only
...
mode is enabled.
2018-08-27 16:42:48 -07:00
Matt Guthaus
01cbc71a2a
Limit sizes for dff_buf too. Add comments about restriction.
2018-07-27 08:17:50 -07:00
Matt Guthaus
b541efe959
Fix wide gnd rail spacing to inverter NMOS by adding size limit to pinv.
2018-07-27 07:23:18 -07:00
Matt Guthaus
f34c4eb7dc
Convert entire OpenRAM to use python3. Works with Python 3.6.
...
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
2018-05-14 16:15:45 -07:00
Matt Guthaus
97c08bce95
Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.
...
Shift s_en buffers even with other cells.
2018-03-23 08:14:09 -07:00
Matt Guthaus
696433b1ec
Add bank_sel to bank_select module as input.
...
Remove reference to control in sram.
Add dff_buf_array to options.
Added inverted DFF
Add variable height pinvbuf
2018-03-23 08:13:39 -07:00