Commit Graph

11 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low 1942ef33ac Merge branch 'dev' into datasheet_gen 2018-11-20 11:23:42 -08:00
Matt Guthaus ca750b698a Uniquify bitcell array 2018-11-16 12:52:22 -08:00
Matt Guthaus e040fd12f9 Bitcell and bitcell array can be named the same. 2018-11-16 12:00:23 -08:00
Matt Guthaus 5e0eb609da Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names. 2018-11-16 11:48:41 -08:00
Jesse Cirimelli-Low 59c0421804 merge dev into datasheet_gen; fixed merge conflict in hierarchy_design.py 2018-11-15 10:45:33 -08:00
Matt Guthaus ff0a7851b7 Fix error when DRC is disabled so it doesn't initialize. 2018-11-13 17:41:32 -08:00
Matt Guthaus ce74827f24 Add new option to enable inline checks at each level of hierarchy. Default is off. 2018-11-13 16:51:19 -08:00
Jesse Cirimelli-Low 3fa1d5522e added DRC/LVS error count to datasheet 2018-11-01 14:02:33 -07:00
Matt Guthaus 6220ea6d47 Update router to work with pin_layout structure. 2018-08-29 15:34:45 -07:00
Matt Guthaus c6503dd771 Modify unit tests to reset options during init_openram so
that they don't use old parameters after a failure.
2018-07-10 16:39:32 -07:00
Matt Guthaus 94db2052dd Consolidate metal pitch rules to new design class 2018-07-09 15:42:46 -07:00