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OpenRAM
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4,821 Commits 4 Branches 63 Tags 78 MiB
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30 Commits

Author SHA1 Message Date
Eren Dogan f8b2c1e9b9 Change OPTS.route_supplies option since there's only one router now 2023-08-02 21:48:29 -07:00
Eren Dogan 54fc34392d Remove unnecessary imports 2023-08-02 21:28:21 -07:00
Eren Dogan 87eca6b7db Use the initial bbox to route supply and signals 2023-08-02 18:01:09 -07:00
Eren Dogan 5b0f97860a Calculate bbox inside the router 2023-08-02 09:30:50 -07:00
Eren Dogan dd152da5c2 Change signal escape router's high-level function name 2023-08-01 11:26:25 -07:00
Eren Dogan 993b47be4c Remove old routers from sram_1bank 2023-08-01 11:22:50 -07:00
Eren Dogan db2a276077 Split graph router class to use it for signal escaping later 2023-07-31 19:43:09 -07:00
Eren Dogan 5de7b9cda7 Make graph router the default supply router 2023-07-24 13:07:43 -07:00
Eren Dogan 53d00f5b34 Merge branch 'dev' into gridless_router 2023-07-18 10:00:00 -07:00
Eren Dogan 5ef964d01f Merge branch 'dev' into gridless_router 2023-07-18 09:31:20 -07:00
Eren Dogan 094e71764a Change option name for the gridless router 2023-07-13 12:16:58 -07:00
Sam Crow b91c628acf Merge branch 'dev' into delay_ctrl 2023-07-06 08:45:03 -07:00
Gary Mejia 9a36cce7ae Fixed formatting on all files 2023-06-14 12:28:36 -07:00
Gary Mejia 692acd2066 Verilog ROM model created for testing 2023-06-12 15:35:54 -07:00
Sam Crow ce622952ef route rbl conditionally 2023-06-08 12:36:31 -07:00
Sam Crow 9fdf8a8341 ommit rbl pins in sram_1bank when appropriate 2023-06-06 13:15:17 -07:00
Sam Crow 2f5d3b6faf Merge branch 'dev' into delay_ctrl 2023-06-05 16:24:48 -07:00
Eren Dogan e1e24f6d06 Rename gridless router 2023-05-29 09:18:55 -07:00
Eren Dogan 909ac6ce68 Add initial files for navigation router 2023-05-04 20:51:30 -07:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
Bugra Onal 1a23d156c0 remove references to bank_sel 2022-08-18 10:33:46 -07:00
Bugra Onal aefe46394c Merge branch 'dev' into multibank 2022-08-12 21:45:26 -07:00
Bugra Onal a361d9f7bb Fixed write_size checks for None 2022-07-28 16:45:58 -07:00
Bugra Onal 30f5638b9f Replaced instances of addr_size with bank_addr 2022-07-28 15:03:41 -07:00
Bugra Onal 24bb6f8c11 Multibank file generation (messy) 2022-07-28 15:03:37 -07:00
Eren Dogan e3fe8c3229 Remove line ending whitespace 2022-07-22 19:52:38 +03:00
samuelkcrow 3526a57864 don't route rbl to conrol logic 2022-07-21 19:35:02 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00