Bugra Onal
d3753556c1
Pin generation instead of parsing
2022-08-18 21:09:48 -07:00
Bugra Onal
eceb35f205
Skip graph exclusions on memchar
2022-08-18 20:38:09 -07:00
Bugra Onal
56879bf48b
Cleanup
2022-08-18 20:35:34 -07:00
Bugra Onal
f0a4665953
Add top process averness
2022-08-18 20:35:02 -07:00
Bugra Onal
efd6da5300
Parse pins from HTML
2022-08-18 12:54:39 -07:00
Bugra Onal
9fba946f18
Characterizer use_model set to false
2022-08-18 12:54:09 -07:00
Bugra Onal
f602c6b263
HTML parsing for fake_sram added
2022-08-12 23:29:33 -07:00
Bugra Onal
bd6621cb88
Increase random value range by 1
2022-08-10 14:21:54 -07:00
Bugra Onal
3f941d2fff
Copy over the CSV read function to fake_sram
2022-08-10 12:59:54 -07:00
Bugra Onal
f8c80999bd
Merge branch 'char' of github.com:VLSIDA/PrivateRAM into char
2022-08-10 12:31:13 -07:00
Bugra Onal
c7975e3274
Use fake sram in memchar
2022-08-10 12:22:47 -07:00
Bugra Onal
ae107b635f
Enable datasheet generation by default
2022-08-10 12:22:47 -07:00
Bugra Onal
2101067e4a
Characterizer options
2022-08-10 12:22:47 -07:00
Bugra Onal
219b29a833
Fake SRAM and Xyce RAW file option
2022-08-10 12:22:47 -07:00
samuelkcrow
8872a3e312
add tests
2022-08-10 12:22:47 -07:00
samuelkcrow
8d1d3c0e90
disable lvs/drc in char and func scripts
2022-08-10 12:22:47 -07:00
samuelkcrow
e621890f78
force netlist only mode in memchar memfunc, rename char and func scripts, add description for func script
2022-08-10 12:22:47 -07:00
samuelkcrow
3e528a3e75
log sim result after func_sim
2022-08-10 12:22:47 -07:00
samuelkcrow
9e29391992
clarify file location message for user
2022-08-10 12:17:14 -07:00
mrg
2adab1ea1a
Initial work on separate delay and func simulation
2022-08-10 12:14:47 -07:00
samuelkcrow
ebe4393d66
reorder sram __init__() argument order for tests that rely on the order
2022-08-10 12:07:09 -07:00
samuelkcrow
34ee709c69
call create() function from sram/__init__
2022-08-10 12:07:07 -07:00
samuelkcrow
2bbd293bf2
clarify file location message for user
2022-08-10 12:06:18 -07:00
samuelkcrow
8793dda40a
characterizer and functional simulator working from command line
2022-08-10 12:06:18 -07:00
samuelkcrow
e2a52ec0f3
Adding characterizer executable
2022-08-10 12:06:18 -07:00
mrg
28128157c0
Initial work on separate delay and func simulation
2022-08-10 12:06:14 -07:00
samuelkcrow
caba726cfe
add pdks and test results to gitignore
2022-08-02 13:44:56 -07:00
mrg
6f696e312e
Revert to old ngspice repo. Other is outdated.
2022-08-02 10:25:23 -07:00
mrg
4b96b539e2
Dockerfile updates
...
Remove conditional bash commands and make one per line.
Change ngspice repo to github.
Fix typo in ngspice commit.
Reduce number of cores in klayout compile.
2022-08-02 10:25:23 -07:00
samuelkcrow
1177df6193
move most of place_instances to base
2022-08-01 10:33:48 -07:00
samuelkcrow
1c8aeaa68a
fix imports
2022-07-27 11:09:10 -07:00
samuelkcrow
2ff9ea4f78
move generic functions from control_logic module to new control_logic_base module
2022-07-26 23:22:02 -07:00
mrg
5db470155e
Fix print errors in code format unit test.
2022-07-26 12:20:15 -07:00
mrg
69d5731d67
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
2022-07-22 13:47:19 -07:00
Matt Guthaus
f1e452c8e3
Merge pull request #150 from erendn/fix_whitespace
...
Fix whitespace
2022-07-22 13:38:48 -07:00
Eren Dogan
03422be48c
Fix carriage return
2022-07-22 19:54:35 +03:00
Eren Dogan
e3fe8c3229
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
Eren Dogan
2a778dca82
Add whitespace check to code format test
2022-07-22 18:22:40 +03:00
Eren Dogan
64c72ee19d
Fix typo
2022-07-22 18:15:27 +03:00
Eren Dogan
449c68ccae
Fix file setup in code format test
2022-07-22 18:11:14 +03:00
mrg
0d616ae072
Merge branch 'dev' into stable
2022-07-21 09:37:24 -07:00
mrg
6707a93c3c
Add fudge factor for bitcell array side rail spacings to fix DRC in freepdk45.
2022-07-20 10:27:30 -07:00
mrg
5ad97aa636
Update README and setpaths with new PYTHONPATH
2022-07-20 10:27:10 -07:00
mrg
3b0533c9c7
v1.2.0
2022-07-17 19:55:05 -07:00
mrg
c406e2a9da
Make macros use same DOCKER_CMD.
2022-07-13 17:19:25 -07:00
mrg
ff7ceaf92d
Fix syntax error for module scope in row/col caps.
2022-07-13 17:19:09 -07:00
mrg
d92c7a634d
Use packages for imports.
...
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
2022-07-13 15:55:57 -07:00
mrg
58ea148d47
Add dlxtn latch for open reg file
2022-06-22 09:53:10 -07:00
mrg
f7738c60a3
Don't install SRAM macros.
2022-06-21 13:53:08 -07:00
mrg
ac86ad0e8a
Move pdk installation inside docker to use Magic from docker image.
2022-06-21 12:10:15 -07:00
Bugra Onal
samuelkcrow
mrg
Eren Dogan