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OpenRAM
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44 Commits

Author SHA1 Message Date
Matt Guthaus 90d1fa7c43 Bitcell supply routing fixes. 
Flatten and simplify 1rw 1r bitcell.
Move bitcell vias to M3 if rotation is limited.
Simplify replica bitcell vdd routing.
 2018-11-30 12:32:13 -08:00
Matt Guthaus 83aadc47c9 Remove layer 230 labels from library cells 2018-11-09 11:12:31 -08:00
Matt Guthaus 05c25eb506 Remove layer 230 labels from library cells 2018-11-09 11:08:20 -08:00
Matt Guthaus 9fe64b486c Remove layer 230 labels from library cells 2018-11-09 11:02:19 -08:00
Matt Guthaus c01f0f5274 Merge branch 'dev' into fix_rbl_cell_connections 2018-11-05 16:38:46 -08:00
Matt Guthaus de6d9d4699 Change freepdk45 rbl cell too. 2018-11-05 11:02:11 -08:00
Hunter Nichols b00fc040a3 Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos. 2018-11-01 12:29:49 -07:00
Hunter Nichols 9321f0461b Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r. 2018-10-31 00:06:34 -07:00
Hunter Nichols 6efe0f56c2 Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array. 2018-10-26 00:08:13 -07:00
Hunter Nichols 8e243258e4 Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell. 2018-10-26 00:08:12 -07:00
Hunter Nichols 4f08062268 Added custom 1rw+1r bitcell. Testing are currently failing. 2018-10-22 17:02:21 -07:00
Matt Guthaus f8fc7c12b3 Remove ms_flop and replace with dff. Might break setup_hold tests. 2018-09-13 11:02:28 -07:00
Matt Guthaus d721fae5b0 Change labels in replica cell for freepdk45 too 2018-09-04 14:33:14 -07:00
Michael Timothy Grimes d8cb3653e0 changing case of pins in handmade cell_6t for freepdk45 2018-05-22 14:19:26 -07:00
Matt Guthaus 85b7b73903 Flip sense amp y axis 2018-04-23 10:19:26 -07:00
Matt Guthaus 269d553857 Move sense amp to tri gate routing to M3... not ideal. 2018-04-23 09:14:18 -07:00
Matt Guthaus e1f4c933e1 Flip sense amp and increase pin size 2018-04-20 17:04:26 -07:00
Matt Guthaus c75eafe085 Fix some errors 2018-04-18 09:37:33 -07:00
Matt Guthaus e2f93a0a99 Fix via overlap DRC error 2018-04-11 15:48:40 -07:00
Matt Guthaus ef99d13f1b Fix via overlap DRC error 2018-04-11 15:46:44 -07:00
Matt Guthaus 6640d3491d Tri gate and array supply to M2 and M3 2018-04-11 15:11:47 -07:00
Matt Guthaus 06c132b695 Fix drc overlap error 2018-04-11 15:00:56 -07:00
Matt Guthaus 21bc5b7d05 Fix drc overlap error 2018-04-11 14:59:04 -07:00
Matt Guthaus 14ff20fc9e Fix drc overlap error 2018-04-11 14:56:59 -07:00
Matt Guthaus d1862eda90 Fix drc overlap error 2018-04-11 14:55:04 -07:00
Matt Guthaus 46c18f53ba Add M2 vias in ms_flop 2018-04-11 14:10:57 -07:00
Matt Guthaus 0e6720be66 Fix write driver gnd pin layer text 2018-04-11 09:34:13 -07:00
Matt Guthaus 4f8ab78ee2 Change write driver supply pins to M2 2018-04-11 09:29:54 -07:00
Matt Guthaus 80829aa0af Sense amp vdd/gnd to M2 2018-04-06 17:15:36 -07:00
Matt Guthaus a35fc1f339 Add contact to cell6t and replica. 2018-04-04 13:18:12 -07:00
Matt Guthaus a0bf5345f8 Mostly working for 1 bank. 2018-03-23 08:14:26 -07:00
Matt Guthaus c020d74f26 Add dff_buf and dff_array modules. 2018-03-23 08:11:51 -07:00
Matt Guthaus 8d9b79dfd8 Add dff_buf for buffered flop arrays. 2018-03-04 16:13:10 -08:00
mguthaus 1297cb4e40 Convert dff to VTG transistors in 45nm. Correct pin order in dff library cell. 2018-02-16 10:40:05 -08:00
Matt Guthaus bab9ae8201 Fix off-grid pin and overlap problems for pins in freepdk dff cell. 2018-02-15 17:54:26 -08:00
Matt Guthaus e66a37c916 Put DFF pins on 2.5nm grid in 45nm. 2018-02-15 11:08:57 -08:00
Matt Guthaus 2d3acb03a1 Add bbox for dff in freepdk45 2018-02-14 17:04:31 -08:00
Matt Guthaus d89e49aecc Add metal2 pins to freepdk45 dff. 2018-02-14 16:58:41 -08:00
Matt Guthaus 0804a1eceb Add new DFF. Create DFF module. Start dff_array, not tested. 2018-02-14 15:16:28 -08:00
Matt Guthaus 512448f9e8 Fix pin names to lower case. Fix write driver DRC errors and LVS error. 2018-01-31 17:37:16 -08:00
Matt Guthaus e06e1691c8 Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
Matt Guthaus d17711c394 Fixed several LVS errors. Bank passes LVS for 2-way and 4-way, but not 1-way or 8-way. 2017-08-24 16:22:14 -07:00
Matt Guthaus cf940fb15d Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
Matt Guthaus f48272bde6 RELEASE 1.0 2016-11-08 09:57:35 -08:00