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OpenRAM
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27 Commits

Author SHA1 Message Date
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg c7d32089f3 Create RBL wordline buffer with correct polarity. 2020-09-17 14:45:49 -07:00
Hunter Nichols 73b2277daa Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
mrg 30976df48f Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
mrg c96a6d0b9d Add no well option. Add stack gates vertical option. 2020-05-11 16:22:08 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
mrg fc85dfe29f Add boundary to all pgates 2020-04-21 15:21:57 -07:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Matt Guthaus 84c7146792 Fix some pep8 errors/warnings in pgate and examples. 2019-10-06 17:30:16 +00:00
Hunter Nichols 2ce7323838 Removed all unused analytical delay functions. 2019-08-06 17:09:25 -07:00
Matt Guthaus ad35f8745e Add direction to pins of all modules 2019-08-06 14:14:09 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 05ad4285af Cleanup pgate code. 
Moved create_netlist and create_layout to the pgate class
from which everything is derived. Modified all pgates
to have consistent debug output and order of init function.
 2019-04-26 12:30:42 -07:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Matt Guthaus 091b4e4c62 Add size commments to spize. Change pdriver stage effort. 2019-01-23 17:27:15 -08:00
Matt Guthaus b58fd03083 Change pbuf/pinv to pdriver in control logic. 2019-01-23 12:03:52 -08:00
Matt Guthaus a418431a42 First draft of sram_factory code 2019-01-16 16:15:38 -08:00
Hunter Nichols ea55bda493 Changed s_en delay calculation based recent control logic changes. 2018-12-05 17:10:11 -08:00
Hunter Nichols 722bc907c4 Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
Matt Guthaus 2ed8fc1506 pgate inputs and outputs are all on M1 for flexible via placement when using gates. 2018-11-28 12:42:29 -08:00
Matt Guthaus 9e0b31d685 Make pand2 and pbuf derive pgate. Initial DRC wrong layout. 2018-11-26 16:19:18 -08:00
Matt Guthaus b440031855 Add netlist only mode to new pgates 2018-11-26 15:29:42 -08:00
Jennifer Eve Sowash bb7773ca7f Editted pbuf.py to pass regression. 2018-11-20 14:39:11 -08:00
Jennifer Sowash b6f1409fb9 Testing to ensure branch is up to date with dev. Added 04_pbuf_test.py and made changes to pbuf.py to align with comments. 2018-11-12 13:24:27 -08:00
Jennifer Sowash 82abd32785 Added pbuf.py to create a single buffer. 2018-11-12 09:53:21 -08:00