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OpenRAM
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28 Commits

Author SHA1 Message Date
Hunter Nichols ad229b1504 Altered indexing of objects in SRAM factory to remove duplications of items using OPTS names. Added smarter bitline name checking. 2019-05-28 16:55:09 -07:00
Hunter Nichols d08181455c Added multiport bitcell support for storage node checks 2019-05-20 22:50:03 -07:00
Hunter Nichols d8617acff2 Merged with dev 2019-05-15 18:48:00 -07:00
Hunter Nichols d54074d68e Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based. 2019-05-07 00:52:27 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Hunter Nichols e292767166 Added graph creation and functions in base class and lower level modules. 2019-04-24 14:23:22 -07:00
Matt Guthaus 25bc3a66ed Add far left option for contact placement in pgates. 2019-04-17 13:41:35 -07:00
Matt Guthaus be20408fb2 Rewrite add_contact to use layer directions. 2019-04-15 18:00:36 -07:00
Hunter Nichols a500d7ee3d Adjusted bitcell analytical delays for multiport cells. 2019-04-09 02:49:52 -07:00
Hunter Nichols 80a325fe32 Added corner information for analytical power estimation. 2019-03-04 19:27:53 -08:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Matt Guthaus a418431a42 First draft of sram_factory code 2019-01-16 16:15:38 -08:00
Hunter Nichols 722bc907c4 Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
Matt Guthaus 90d1fa7c43 Bitcell supply routing fixes. 
Flatten and simplify 1rw 1r bitcell.
Move bitcell vias to M3 if rotation is limited.
Simplify replica bitcell vdd routing.
 2018-11-30 12:32:13 -08:00
Hunter Nichols bad55cfd05 Merged with dev. Fixed merge conflict. 2018-11-09 17:18:19 -08:00
Hunter Nichols 8957c556db Added sense amp enable delay calculation. 2018-11-08 23:54:18 -08:00
Matt Guthaus 31eff6f24e Merge branch 'dev' into multiport_layout 2018-11-08 18:00:28 -08:00
Matt Guthaus ef2ed9a92c Simplify bl and br name lists. 2018-11-08 15:48:49 -08:00
Michael Timothy Grimes 6711630463 Altering the routing slightly in the column mux to give the gnd contacts a wider berth. This prevents drc errors when the bitlines are close to the edge of the cell. 2018-11-02 05:59:47 -07:00
Michael Timothy Grimes dc96d86082 Optimizations to pbitcell spacings 2018-11-01 07:58:20 -07:00
Hunter Nichols 98a00f985b Changed the analytical delay model to accept multiport options. Little substance to the values generated. 2018-10-26 00:08:13 -07:00
Michael Timothy Grimes 1a0568f244 Updating comments and cleaning up code for pbitcell. 2018-10-21 19:10:04 -07:00
Matt Guthaus 7591f25a2e Merge branch 'dev' into supply_routing 2018-10-20 14:29:19 -07:00
Matt Guthaus 4bf1e206e2 Merge branch 'dev' into supply_routing 2018-10-17 09:47:18 -07:00
Matt Guthaus a094db9077 Merge branch 'multiport' into supply_routing 2018-10-11 09:56:38 -07:00
Matt Guthaus a2b1d025ab Merge multiport 2018-10-08 11:45:50 -07:00
Matt Guthaus 68b30d601e Move bitcells to their own directory in preparation for custom multiport cells. 2018-10-05 08:09:09 -07:00