11 Commits

Author	SHA1	Message	Date
Hunter Nichols	f6eefc1728	Added updated analytical characterization with combined models	2019-04-02 01:09:31 -07:00
Hunter Nichols	0e96648211	Added linear corner factors in analytical delay model.	2019-03-04 00:42:18 -08:00
Matt Guthaus	091b4e4c62	Add size commments to spize. Change pdriver stage effort.	2019-01-23 17:27:15 -08:00
Matt Guthaus	b58fd03083	Change pbuf/pinv to pdriver in control logic.	2019-01-23 12:03:52 -08:00
Matt Guthaus	a418431a42	First draft of sram_factory code	2019-01-16 16:15:38 -08:00
Hunter Nichols	ea55bda493	Changed s_en delay calculation based recent control logic changes.	2018-12-05 17:10:11 -08:00
Matt Guthaus	2ed8fc1506	pgate inputs and outputs are all on M1 for flexible via placement when using gates.	2018-11-28 12:42:29 -08:00
Matt Guthaus	9e0b31d685	Make pand2 and pbuf derive pgate. Initial DRC wrong layout.	2018-11-26 16:19:18 -08:00
Matt Guthaus	b440031855	Add netlist only mode to new pgates	2018-11-26 15:29:42 -08:00
Matt Guthaus	2eff166527	Rotate vias in pand2	2018-11-26 14:05:04 -08:00
Matt Guthaus	8fba32ca12	Add pand2 draft	2018-11-26 13:45:22 -08:00