OpenRAM

Commit Graph

Author	SHA1	Message	Date
Matt Guthaus	6220ea6d47	Update router to work with pin_layout structure.	2018-08-29 15:34:45 -07:00
Matt Guthaus	138a70fc23	Add place_inst routine. Separate create netlist and layout in some modules.	2018-08-27 10:42:40 -07:00
Matt Guthaus	f34c4eb7dc	Convert entire OpenRAM to use python3. Works with Python 3.6. Major changes: Remove mpmath library and use numpy instead. Convert bytes to new bytearrays. Fix class name check for duplicate gds instances. Add explicit integer conversion from floats. Fix importlib reload from importlib library Fix new key/index syntax issues. Fix filter and map conversion to lists. Fix deprecation warnings. Fix Circuits vs Netlist in Magic LVS results. Fix file closing warnings.	2018-05-14 16:15:45 -07:00
Matt Guthaus	bab92fcf38	Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works.	2018-03-23 08:13:20 -07:00
Matt Guthaus	b867e163a6	Move label pins to center like layout pins. Rework of control logic with vertical poly. Passes DRC/LVS. Single bank passing DRC.	2018-03-23 08:12:59 -07:00
Matt Guthaus	7293eb33bc	Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev	2018-03-02 10:30:16 -08:00
Matt Guthaus	2b839d34a3	Get rid of netgen error of undefined dlatch. Fix sp_read to find correct subckt name and pins.	2018-02-27 08:59:46 -08:00
Hunter Nichols	62ad30e741	Added initial version of analytical power esitmation. Loops through instances but power estimate is not accurate.	2018-02-22 19:35:54 -08:00
Hunter Nichols	beb7dad9bc	Added corner paramters to power functions. This commit does not compile (sorry)	2018-02-22 00:15:55 -08:00
Hunter Nichols	d4a0f48d4f	Added power calculations for inverter. Still testing.	2018-02-21 19:51:21 -08:00
Matt Guthaus	7100d6f904	Organize top-level files into subdirs.	2018-02-09 10:25:24 -08:00

11 Commits