19d46f5954
Finalized separation of netlist/layout creation.
2018-08-27 14:18:32 -07:00
0f8da1510e
Reverting pin name changes of precharge cell and array back to 'bl' and 'br'. Also clarifying bl and br init parameters to reflect that they refer to the bitcell lines.
2018-08-18 15:27:07 -07:00
040340b49f
editted naming convention on precharge to accommodate multiport
2018-08-15 02:14:45 -07:00
5666ee6635
altered precharge module to accomodate bitlines from pbitcell, and altered unit test to test both bitcell and pbitcell configurations
2018-08-05 19:46:05 -07:00
8f131ddb2f
commiting changes from most recent pull from dev
2018-05-22 17:30:51 -07:00
766042fe69
changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit
2018-05-22 14:16:51 -07:00
f34c4eb7dc
Convert entire OpenRAM to use python3. Works with Python 3.6.
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Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
2018-05-14 16:15:45 -07:00
a6c2e77bcf
Move precharge and column mux cells to pgate directory.
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Move gnd to M3 in column mux.
Create column mux cell unit test.
2018-04-06 17:15:14 -07:00
Matt Guthaus
Michael Timothy Grimes
Michael Timothy Grimes