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OpenRAM
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34 Commits

Author SHA1 Message Date
Hunter Nichols d0e6dc9ce7 First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
Hunter Nichols 62ad30e741 Added initial version of analytical power esitmation. Loops through instances but power estimate is not accurate. 2018-02-22 19:35:54 -08:00
Hunter Nichols d4a0f48d4f Added power calculations for inverter. Still testing. 2018-02-21 19:51:21 -08:00
Hunter Nichols 179a27b0e3 Added some power functions. 2018-02-20 18:22:23 -08:00
Hunter Nichols 8ea384a761 Fixed merging issues with power branch 2018-02-14 15:21:42 -08:00
Matt Guthaus f86985821a Begin modifications for corner-based characterization. Made stimuli.py a class. Golden output files are not updated. 2018-02-09 15:33:03 -08:00
Matt Guthaus d684189241 Don't output text in SRAM during unit test. 2018-02-08 14:58:55 -08:00
Matt Guthaus 17716191c1 Clean up time statements in openram output 2018-02-08 13:11:18 -08:00
Matt Guthaus 6c89f7965d Refactor openram.py. 2018-02-08 12:47:19 -08:00
mguthaus e01d5b7c61 Disable virtual connects at top level LVS with Calibre. 2018-02-05 14:52:51 -08:00
Matt Guthaus 84b42b0170 Fix bug in trim netlist. Add info comments to spice netlist and trimmed netlist. Increase verbosity for simulations. 2018-02-02 19:33:07 -08:00
Matt Guthaus d6d96907ef Route to the right in the bank decode for DRC. 2018-02-02 15:50:45 -08:00
Hunter Nichols db4913dd9c Added skeleton code for analytical power in functions with analytical delay. 2018-02-02 12:31:34 -08:00
Hunter Nichols 56f7caf59f Added first test power model to sram 2018-02-02 12:31:33 -08:00
Matt Guthaus 490a70dee9 Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file. 2018-01-19 16:38:19 -08:00
Matt Guthaus 9a4b2b4341 Revised LEF and Verilog generation. Does not read GDS for speed improvements. 2017-12-19 09:01:24 -08:00
Matt Guthaus abee235963 Rewrite the parameterized transistor and gate classes. 
Changes propagate through all designs.
All modules use instance and layout pins.
 2017-12-12 15:04:01 -08:00
Matt Guthaus 107cad15a1 Change layout function names to be consistent. 2017-11-30 12:01:04 -08:00
mguthaus 09ca8ba17d Improve output format. Rename option to be more sensible. 2017-11-22 15:57:29 -08:00
Matt Guthaus 29c5ab48f0 Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
Matt Guthaus 95f1a24f72 Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
Matt Guthaus 788f3d9122 4-bank SRAMs are now working. 2017-10-04 18:05:45 -07:00
Matt Guthaus 21c77645d3 Remove LVS correspondence points for multibank in single bank. 2017-09-29 16:44:24 -07:00
Matt Guthaus e06e1691c8 Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
Matt Guthaus d29dd03373 SRAM single bank passing DRC/LVS. 2017-09-13 15:46:41 -07:00
Matt Guthaus cf940fb15d Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
Matt Guthaus 20d8c0bc45 Improved characterizer. 2017-07-06 08:42:25 -07:00
mguthaus e92cb9ecef Removed array_type from ms_flop_array since it is extraneous code. 2017-07-03 12:08:50 -07:00
mguthaus f32912f07c Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity. 2017-06-02 11:11:57 -07:00
Matt Guthaus 34e180b901 Analytical delay model from Bin Wu. Unit test not passing. 2017-05-30 12:50:07 -07:00
Matt Guthaus 81ab1f1f82 Change layer order for add_wire 2016-11-17 14:05:50 -08:00
Bin wu 072a65a511 add rotate_scale function in vector and use it everywhere 2016-11-11 14:33:19 -08:00
Matt Guthaus e1c3d77a5d Removed import cell since cell is removed from simplified txt file 2016-11-09 12:20:52 -08:00
Matt Guthaus f48272bde6 RELEASE 1.0 2016-11-08 09:57:35 -08:00