13 Commits

Author	SHA1	Message	Date
samuelkcrow	6a8a76dd23	Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into no_rbl	2022-12-14 08:13:08 -08:00
Eren Dogan	96e57507bf	Add copyright check to code format test	2022-11-30 14:50:43 -08:00
Eren Dogan	fccdc3c45b	Use library imports globally	2022-11-27 13:01:20 -08:00
Eren Dogan	e718106d87	Change is_unit_test to False by default	2022-11-21 14:52:57 -08:00
samuelkcrow	8bc3903a04	remove end caps from replica column (will not pass sky130 drc)	2022-09-26 14:23:09 -07:00
Eren Dogan	e3fe8c3229	Remove line ending whitespace	2022-07-22 19:52:38 +03:00
mrg	d92c7a634d	Use packages for imports. ... Must set PYTHONPATH to include OPENRAM_HOME now. Reorganizes subdirs as packages. Rewrites unit tests to use packages. Update README.md with instructions, dependencies etc. Update sky130 module imports. Change tech specific package from modules to custom.	2022-07-13 15:55:57 -07:00
Matt Guthaus	30fc81a1f0	Update copyright year.	2021-01-22 11:23:28 -08:00
mrg	f729e9fca7	Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions.	2020-11-20 16:56:07 -08:00
mrg	29ac541b28	Refactor dynamic cell name to utilize base class	2020-11-03 13:18:46 -08:00
mrg	da721a677d	Remove EOL whitespace globally	2020-11-03 06:29:17 -08:00
mrg	99e252d6d4	Update interface of RBL array	2020-08-17 17:19:07 -07:00
mrg	f2c45a230e	Add new replica column test. Add more skip tests.	2020-06-10 11:00:00 -07:00