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luke/OpenRAM
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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-01 18:48:10 +02:00
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4,998 Commits 5 Branches 63 Tags
4c93ec5608b2fb4e59139fcb902d8e13d559e92c
Commit Graph
61 Commits
Author SHA1 Message Date
mrg 224e359208 Fix pin order for replica array 2020-08-18 15:59:05 -07:00
mrg 59d65c46c3 Fix bug in not adding RBLs in local bitcell array 2020-08-18 15:11:10 -07:00
mrg 2643a96f97 Order inputs wordline, bitline, supply 2020-08-18 14:29:36 -07:00
mrg 99e252d6d4 Update interface of RBL array 2020-08-17 17:19:07 -07:00
mrg b1e55f9072 Add local bitcell array 2020-08-17 15:14:42 -07:00
mrg 8e890c2014 Replica bitcell with all the fixings 2020-08-11 15:00:29 -07:00
mrg eef97ff215 Reabstracting bit and word line names. 2020-08-06 11:17:49 -07:00
mrg 2fa561f98f Local bitcell array edits. Skip test by default. 2020-07-29 10:08:13 -07:00
mrg c260297366 Allow replica_bitcell_array without the replica columns for local wordlines. 2020-07-27 16:22:21 -07:00
mrg 2991534d3f Drafting local bitline stuff. 2020-07-23 17:15:39 -07:00
mrg e1967dc548 Draft local and global arrays. Ensure rows before cols in usage. 2020-07-23 14:43:14 -07:00
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