mirror of https://github.com/VLSIDA/OpenRAM.git
67 lines
2.3 KiB
Python
67 lines
2.3 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from bitcell_base_array import bitcell_base_array
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from tech import drc, spice
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from globals import OPTS
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from sram_factory import factory
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class local_bitcell_array(bitcell_base_array):
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"""
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A local wordline array is a bitcell array with a wordline driver.
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This can either be a single aray on its own if there is no hierarchical WL
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or it can be combined into a larger array with hierarchical WL.
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"""
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def __init__(self, name, rows, cols):
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super().__init__(name, rows, cols)
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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# We don't offset this because we need to align
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# the replica bitcell in the control logic
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# self.offset_all_coordinates()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array("bit_r{0}_c{1}")
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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self.bit_array = factory.create(module_type="bitcell_array",
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rows=self.rows,
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cols=self.cols,
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column_offset=self.column_offset)
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self.add_mod(self.bit_array)
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self.wl_array = factory.create(module_type="wordline_driver_array",
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rows=self.rows,
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cols=self.cols)
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self.add_mod(self.wl_array)
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def create_instances(self):
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""" Create the module instances used in this design """
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self.bitcell_inst = self.add_inst(mod=self.bitcell_array)
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self.connect_inst(self.get_bitcell_pins(row, col))
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self.wl_inst = self.add_inst(mod=self.wl_array)
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self.connect_inst(self.get_bitcell_pins(row, col))
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