Jesse Cirimelli-Low
5222224936
route supplies from endcaps to power ring
2026-05-13 16:45:52 -07:00
Jesse Cirimelli-Low
c7f3ac33cd
sky130 cypress dp working with offset relative to crba
2026-04-27 17:24:13 -07:00
Jesse Cirimelli-Low
cb7f117daa
squash commits
2026-04-22 01:33:47 -07:00
Jesse Cirimelli-Low
515591a422
dual port rba lvs clean again with cell library changes
2026-04-14 14:48:26 -07:00
Jesse Cirimelli-Low
53d53ec271
checkpoint from tt submission
2026-01-14 12:08:26 -08:00
Jesse Cirimelli-Low
4ce6e0538b
fix col_cap array for dummu compatability ...bitcells next
2025-03-06 02:05:43 -08:00
Jesse Cirimelli-Low
f3c1c5fbb2
Merge branch 'singleport_refactor' into array_gen
2025-02-24 23:26:28 -08:00
Eren Dogan
0a1de57cae
Update copyright year
2024-01-03 14:32:44 -08:00
Jesse Cirimelli-Low
0cba6a6050
single port sky130 crba passing lvs
2023-08-30 20:59:02 -07:00
Jesse Cirimelli-Low
8794070ebc
various refactor changes
2023-08-28 12:31:55 -07:00
Eren Dogan
e5fc25da6f
Update copyright year
2023-01-28 22:56:27 -08:00
Eren Dogan
96e57507bf
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
Eren Dogan
fccdc3c45b
Use library imports globally
2022-11-27 13:01:20 -08:00
mrg
d92c7a634d
Use packages for imports.
...
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
2022-07-13 15:55:57 -07:00
mrg
64f2f90664
Rework replica_bitcell_array supplies
...
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
2022-04-19 08:50:11 -07:00
mrg
0c3ee643ab
Remove add_mod and add module whenever calling add_inst.
2021-11-22 11:33:27 -08:00
Matt Guthaus
30fc81a1f0
Update copyright year.
2021-01-22 11:23:28 -08:00
mrg
01d312d65c
Refactor add power pins
2021-01-13 10:57:12 -08:00
mrg
bad1274bdb
Use internal name for col/row caps. gds ordered read enabled.
2020-12-03 10:03:47 -08:00
mrg
27a652ac1b
Fix bounding box of cap arrays
2020-11-20 16:54:53 -08:00
mrg
86799ae3ff
Small bug fixes related to new name mapping.
2020-11-16 13:42:42 -08:00
mrg
8021430122
Fix pbitcell erros
2020-11-13 15:55:55 -08:00
mrg
8be1436d51
Use OPTS.bitcell everywhere
2020-11-05 16:55:08 -08:00
mrg
da721a677d
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
mrg
20be7caf98
Make conditional wl and bl for dummy rows/cols.
2020-10-15 13:56:37 -07:00
mrg
6a1f12b62d
Refactored to utilize OOP
2020-10-13 11:07:31 -07:00
mrg
c260297366
Allow replica_bitcell_array without the replica columns for local wordlines.
2020-07-27 16:22:21 -07:00
mrg
e1967dc548
Draft local and global arrays. Ensure rows before cols in usage.
2020-07-23 14:43:14 -07:00
mrg
0926eab9f5
PEP8 formatting
2020-06-22 12:55:18 -07:00
mrg
5514996708
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
Joey Kunzler
7505fa5aef
update for end caps
2020-05-27 20:03:11 -07:00
Jesse Cirimelli-Low
Eren Dogan
Eren Dogan
mrg
Joey Kunzler