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OpenRAM
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3,355 Commits 4 Branches 63 Tags 78 MiB
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3355 Commits

Author SHA1 Message Date
mrg 31d3e6cb26 Change LWL layers 2021-04-07 16:07:56 -07:00
mrg e0024fa79a Add verbosity to error output 2021-04-07 16:07:56 -07:00
mrg bd28a7a93b Merge branch 'sky130_fixes' into dev 2021-04-01 16:48:22 -07:00
mrg 014c95f761 Add accounting output to ngspice 2021-04-01 16:48:15 -07:00
mrg c7f99aef2c Add functional comment to aid debugging checks. 2021-03-31 12:14:20 -07:00
mrg 7e29dd7ff2 Reduce verbosity of routing info 2021-03-31 09:38:06 -07:00
mrg b9086dbbe5 Add unit test times to output. 2021-03-26 06:56:58 -07:00
mrg e681806f0d Update to 24 threads. 2021-03-25 10:02:34 -07:00
mrg 6e2f60353c Add wells to driver stages. Remove unnecessary height/center in control logic. 2021-03-25 10:00:24 -07:00
mrg 4a40e96f6d Control logic route changes. 
Move wl_en to top control signal.
Route wl_en directly to port_address.
Reorder input bus to bank.
 2021-03-24 14:32:10 -07:00
mrg e144f03b23 Add status for supply routing. 2021-03-24 11:15:59 -07:00
mrg fae72ca993 Test new archive options for github actions. 2021-03-23 13:06:36 -07:00
mrg 7b270514e1 Update multithreaded regression. 
Only do 2 threads for 30 tests.
Don't archive results since they are purged anyways.
16 threads for regression.
Purge temp during regression.
 2021-03-23 10:45:56 -07:00
mrg 671470f5f2 Skywater changes. 
Default 1 thread and no temp subdirectory.
Add skywater setup/hold golden data
Add CLI option for simulation threads (-m)
Add compatibility mode option and nomodcheck for ngspice to speed up sky130 model loading.
Make subdir when using default /tmp dir.
Pass num_threads so temp subdirs are created.
 2021-03-22 15:48:14 -07:00
mrg b6f3fbdd1f Use OPTS.precharge instead of hard coded precharge. 2021-03-15 09:44:14 -07:00
mrg db118beeba Zoom parameter should be optional in tech files. 2021-03-02 13:38:09 -08:00
mrg da3a100301 Try new wildcard for archive path. 2021-03-02 09:28:59 -08:00
mrg 90cb9f581f Fixes to get hspice delay test to pass. 2021-03-02 09:28:41 -08:00
mrg fb953c19e8 Remove option that causes errors and is unused. 2021-03-01 16:36:27 -08:00
mrg 13bdae2e30 Merge remote-tracking branch 'private/dev' into control-logic-pull 2021-03-01 15:47:33 -08:00
mrg 049d3ffcaf Remove extra test file 2021-03-01 15:25:39 -08:00
mrg 9e7c04a43a Merge lekez2005 changes WITHOUT control logic change. 2021-03-01 15:19:30 -08:00
mrg 1614dc140d Remove tab 2021-03-01 14:59:49 -08:00
mrg 96faf06b7c Each job must checkout with multiple runners 2021-03-01 14:58:55 -08:00
mrg 01094ae4f0 Don't upload coverage artifacts 2021-03-01 14:56:56 -08:00
mrg f31125645e Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2021-03-01 14:06:51 -08:00
mrg 4ab694033d Merge remote-tracking branch 'bvhoof/dev' into dev 2021-03-01 12:16:26 -08:00
mrg ae8926c5c2 Merge remote-tracking branch 'private/dev' into dev 2021-03-01 12:12:44 -08:00
mrg bedd1b3d15 Don't need to cleanup as checkout does it. 2021-03-01 11:40:58 -08:00
mrg 5ab67214e5 Make sure to add path when source and target 2021-03-01 11:37:42 -08:00
mrg 7c15773e17 Only remove temp dirs, erase coverage 2021-03-01 10:51:09 -08:00
mrg 27c197026f Only remove temp dirs, erase coverage 2021-03-01 10:50:37 -08:00
mrg 5b6bfce7e0 Add steps 2021-03-01 10:37:33 -08:00
mrg c6baef1c59 Remove tabs 2021-03-01 10:34:46 -08:00
mrg 0ba1ceff6a Separate checkout step 2021-03-01 10:33:57 -08:00
mrg f7d66b7d2c Update workflow syntax 2021-03-01 10:31:32 -08:00
mrg 7355fc91f8 Update workflow syntax 2021-03-01 10:28:47 -08:00
mrg 0556b931a9 Update workflow syntax 2021-03-01 10:27:56 -08:00
mrg ec783f58b8 Update workflow syntax 2021-03-01 10:22:30 -08:00
mrg 26eed77de0 Update workflow syntax 2021-03-01 10:20:48 -08:00
mrg 59915962a0 Update workflow syntax 2021-03-01 10:19:36 -08:00
mrg ab0b9ca37b Fix syntax error in workflow 2021-03-01 10:15:33 -08:00
mrg ef78ad7249 Upload workflow 2021-03-01 10:12:37 -08:00
Bob Vanhoof f5a9ab3b2c cleanup clutter 2021-03-01 15:23:57 +01:00
Bob Vanhoof fde8794282 calibre pex modifications to run hierarchical pex 2021-03-01 09:56:25 +01:00
ota2 f6afef8d4a rbl_bl_delay_bar to rbl_bl_delay for write enable 2021-02-27 19:30:37 -05:00
ota2 9d025604ff Simulate calibre extracted netlists without requiring extra layout ports 2021-02-27 19:29:18 -05:00
ota2 9a2987ad07 Add spectre simulator 2021-02-27 19:25:00 -05:00
ota2 48bc47c686 Set pin label size to use zoom factor from tech specifications 2021-02-27 18:30:57 -05:00
ota2 15e57d89ca fix end subckt typo 2021-02-27 18:28:07 -05:00