OpenRAM

Commit Graph

Author	SHA1	Message	Date
Michael Timothy Grimes	f1560375fc	Altering control logic for read ports and write ports, by including only read or write specific circuitry. Altering replica bitline layout to support multiport	2018-09-25 20:00:25 -07:00
Michael Timothy Grimes	e0b9989d85	Adding replica_pbitcell and test for multi-ported purposes. Altering replica bitline and test to accomodate.	2018-09-13 01:42:06 -07:00
Matt Guthaus	41fba9d27c	Add sketch for power grid routing code	2018-08-29 15:34:16 -07:00
Matt Guthaus	c6503dd771	Modify unit tests to reset options during init_openram so that they don't use old parameters after a failure.	2018-07-10 16:39:32 -07:00
Matt Guthaus	d4cd8aff15	Change permissions of tests	2018-05-14 16:36:58 -07:00
Matt Guthaus	f34c4eb7dc	Convert entire OpenRAM to use python3. Works with Python 3.6. Major changes: Remove mpmath library and use numpy instead. Convert bytes to new bytearrays. Fix class name check for duplicate gds instances. Add explicit integer conversion from floats. Fix importlib reload from importlib library Fix new key/index syntax issues. Fix filter and map conversion to lists. Fix deprecation warnings. Fix Circuits vs Netlist in Magic LVS results. Fix file closing warnings.	2018-05-14 16:15:45 -07:00
mguthaus	c1c1ba38a3	Fix unit test to have fanout.	2018-02-16 11:53:38 -08:00
Matt Guthaus	2413304f4e	Update replica bitline test for new parameters. Add small test and a larger test.	2018-02-07 15:15:19 -08:00
Matt Guthaus	56770f558f	Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds.	2018-01-29 16:59:29 -08:00
Matt Guthaus	7a172873a3	Update unit tests to load verify after config file. Start magic DRC.	2018-01-12 10:24:49 -08:00
Matt Guthaus	abee235963	Rewrite the parameterized transistor and gate classes. Changes propagate through all designs. All modules use instance and layout pins.	2017-12-12 15:04:01 -08:00

11 Commits