14 Commits

Include renames

Author	SHA1	Message	Date
mrg	b7c43ae674	Fix 1w/1r example	2020-07-23 14:17:13 -07:00
mrg	2011974e01	Make drc and lvs errors a member variable. Run only once.	2020-07-13 12:49:24 -07:00
jcirimel	101eb28112	revert example scn4m to non netlist only	2020-02-09 23:52:11 -08:00
Jesse Cirimelli-Low	b107934672	fix styling	2020-02-06 12:15:52 +00:00
Matt Guthaus	be4893839b	Remove old drc/lvs override name	2019-12-16 10:05:52 -08:00
Matt Guthaus	0cdd3af1aa	Change default nominal corners to false and enable in test config.	2019-11-29 12:08:53 -08:00
Matt Guthaus	84c7146792	Fix some pep8 errors/warnings in pgate and examples.	2019-10-06 17:30:16 +00:00
Matt Guthaus	07ecf52b9f	Add giant example for front-end mode	2019-04-01 15:49:01 -07:00
Matt Guthaus	74f904a509	Cleanup options for front-end. Improve info output.	2019-04-01 10:35:17 -07:00
Matt Guthaus	c3e074c069	Add option for routing supplies. Off by default, but enabled in unit test config files.	2019-04-01 09:58:59 -07:00
Matt Guthaus	1f1426b97c	Add auto-detect of custom bitcells	2019-02-25 16:10:34 -08:00
Matt Guthaus	4577d380f9	Add example 1w/1r	2019-02-24 09:57:34 -08:00
Matt Guthaus	82a09be026	Move inspect into if statement for runtime	2019-01-30 08:42:25 -08:00
Matt Guthaus	5de7ff3773	Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.	2019-01-11 14:15:16 -08:00