OpenRAM/compiler/example_configs
Matt Guthaus c3e074c069 Add option for routing supplies. Off by default, but enabled in unit test config files. 2019-04-01 09:58:59 -07:00
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big_config_scn4m_subm.py Add option for routing supplies. Off by default, but enabled in unit test config files. 2019-04-01 09:58:59 -07:00
example_config_1rw_1r_scn4m_subm.py Add option for routing supplies. Off by default, but enabled in unit test config files. 2019-04-01 09:58:59 -07:00
example_config_1w_1r_scn4m_subm.py Add auto-detect of custom bitcells 2019-02-25 16:10:34 -08:00
example_config_freepdk45.py Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench. 2019-01-11 14:15:16 -08:00
example_config_scn4m_subm.py Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench. 2019-01-11 14:15:16 -08:00
medium_config_scn4m_subm.py Add option for routing supplies. Off by default, but enabled in unit test config files. 2019-04-01 09:58:59 -07:00