OpenRAM

Commit Graph

Author	SHA1	Message	Date
Matt Guthaus	9d5e5086a1	Add new extra design class with additional hierarchy for shared design rules	2018-07-09 15:43:26 -07:00
Matt Guthaus	94db2052dd	Consolidate metal pitch rules to new design class	2018-07-09 15:42:46 -07:00
Matt Guthaus	2833b706c7	Fix duplicate name check for some modules by checking if name is a substring. Allows pbitcell to pass.	2018-06-29 09:23:23 -07:00
Matt Guthaus	f34c4eb7dc	Convert entire OpenRAM to use python3. Works with Python 3.6. Major changes: Remove mpmath library and use numpy instead. Convert bytes to new bytearrays. Fix class name check for duplicate gds instances. Add explicit integer conversion from floats. Fix importlib reload from importlib library Fix new key/index syntax issues. Fix filter and map conversion to lists. Fix deprecation warnings. Fix Circuits vs Netlist in Magic LVS results. Fix file closing warnings.	2018-05-14 16:15:45 -07:00
Matt Guthaus	bab92fcf38	Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works.	2018-03-23 08:13:20 -07:00
Hunter Nichols	d0e6dc9ce7	First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.	2018-02-26 16:32:28 -08:00
Hunter Nichols	62ad30e741	Added initial version of analytical power esitmation. Loops through instances but power estimate is not accurate.	2018-02-22 19:35:54 -08:00
Hunter Nichols	beb7dad9bc	Added corner paramters to power functions. This commit does not compile (sorry)	2018-02-22 00:15:55 -08:00
Hunter Nichols	d4a0f48d4f	Added power calculations for inverter. Still testing.	2018-02-21 19:51:21 -08:00
Hunter Nichols	179a27b0e3	Added some power functions.	2018-02-20 18:22:23 -08:00
Matt Guthaus	7100d6f904	Organize top-level files into subdirs.	2018-02-09 10:25:24 -08:00

11 Commits