18 Commits

Author	SHA1	Message	Date
mrg	17d144b5b5	Clean up multiport test options to be consistent.	2019-07-12 10:39:55 -07:00
mrg	b841fd7ce3	Replica bitcell array with arbitrary RBLs working	2019-07-10 15:56:51 -07:00
mrg	b9d993c88b	Add dummy bitcell module. ... Modify bitcell logic to guess if bitcell is not "bitcell" No longer need to specify replica (and dummy) bitcell explicitly Add support for 1 or 2 port replica array.	2019-07-05 12:58:52 -07:00
mrg	8b0b2e2817	Merge branch 'dev' into rbl_revamp	2019-07-03 14:05:28 -07:00
Hunter Nichols	4e08e2da87	Merged and fixed conflicts with dev	2019-06-25 16:55:50 -07:00
mrg	d8baa5384d	Remove useless comments. Add missing copyright.	2019-06-14 10:13:13 -07:00
Matt Guthaus	6e044b776f	Merge branch 'pep8_cleanup' into dev	2019-06-14 08:47:10 -07:00
Matt Guthaus	a234b0af88	Fix space before comment	2019-06-14 08:43:41 -07:00
mrg	d789f93743	Add debug runner during individual tests.	2019-05-31 10:51:42 -07:00
Hunter Nichols	d8617acff2	Merged with dev	2019-05-15 18:48:00 -07:00
Matt Guthaus	0f03553689	Update copyright to correct years.	2019-05-06 06:50:15 -07:00
Matt Guthaus	3f9a987e51	Update copyright. Add header to all OpenRAM files.	2019-04-26 12:33:53 -07:00
Hunter Nichols	e292767166	Added graph creation and functions in base class and lower level modules.	2019-04-24 14:23:22 -07:00
Matt Guthaus	0354e2dfb7	Rename config_20 to config since it is used in all tests	2019-03-08 10:47:41 -08:00
Matt Guthaus	09a429aef7	Update unit tests to all use the sram_factory	2019-03-06 14:12:24 -08:00
Matt Guthaus	6dd959b638	Fix error in 8mux test. Fix comment in all tests.	2018-11-02 16:34:26 -07:00
Hunter Nichols	6efe0f56c2	Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.	2018-10-26 00:08:13 -07:00
Hunter Nichols	8e243258e4	Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell.	2018-10-26 00:08:12 -07:00