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OpenRAM
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3,109 Commits 4 Branches 63 Tags 78 MiB
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8 Commits

Author SHA1 Message Date
mrg 35c162acbd Use internal pin names in path names for signal traces. 2020-11-19 08:45:09 -08:00
mrg 902b92223f Small fix for finding pin names in timing graph. 2020-11-16 13:57:31 -08:00
mrg 86799ae3ff Small bug fixes related to new name mapping. 2020-11-16 13:42:42 -08:00
mrg 1d729e8f02 Move pin name mapping to layout class. 2020-11-16 11:04:03 -08:00
mrg e4bc2c4914 Update property settings with getters/setters 2020-11-14 08:08:42 -08:00
mrg 8021430122 Fix pbitcell erros 2020-11-13 15:55:55 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00