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OpenRAM
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12 Commits

Author SHA1 Message Date
Matt Guthaus 7cca6b4f69 Add back scn3me_subm support 
Add back scn3me_subm tech files
Update cells to be DRC clean with rule 5.5.b
Allow magic for FreePDK45 but not debugged.
Revert to older Magic tech file for SCN3ME_SUBM
 2019-06-03 15:27:37 -07:00
Matt Guthaus 1a54fd0d1c Remove scn3me_subm since it does not have 4 metal layers 2019-03-11 14:20:02 -07:00
Matt Guthaus 4fc9278b73 Convert bounding box layer for SCMOS to bb, gds layer 63. 2018-09-04 13:05:21 -07:00
Matt Guthaus 269d553857 Move sense amp to tri gate routing to M3... not ideal. 2018-04-23 09:14:18 -07:00
Matt Guthaus c75eafe085 Fix some errors 2018-04-18 09:37:33 -07:00
Matt Guthaus 6640d3491d Tri gate and array supply to M2 and M3 2018-04-11 15:11:47 -07:00
Matt Guthaus c63eb3be3b Fixed bug with missing tri gate via. 2018-01-29 17:29:30 -08:00
Matt Guthaus fb0355ebaf Duplicate gnd label on metal1 pin in tri gate. 2018-01-24 13:20:34 -08:00
Matt Guthaus d84242719b Change pin names in trigate and write_driver. 2018-01-24 13:12:36 -08:00
Matt Guthaus fb2ed1d46c Add wells to fix DRC errors in SCMOS library cells. 2018-01-22 16:28:20 -08:00
Matt Guthaus cf940fb15d Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
Matt Guthaus f48272bde6 RELEASE 1.0 2016-11-08 09:57:35 -08:00