9 Commits

Author	SHA1	Message	Date
mrg	e6a009312e	Move mem reg before usage for compatibility	2021-10-13 09:46:02 -07:00
mrg	67877175b2	Fix error in no spare column verilog	2021-06-18 08:41:26 -07:00
mrg	d43edd95e4	Update golden tests for verilog	2021-05-06 19:56:22 -07:00
mrg	789a8a1cf0	Update golden verilog results	2021-05-05 15:37:27 -07:00
mrg	5b556e6ef5	Update unit test results with new Verilog models.	2021-04-15 15:48:20 -07:00
Matt Guthaus	9f54afbf2c	Fix capitalization in verilog golden files	2019-08-21 14:29:57 -07:00
Matt Guthaus	d0f04405a6	Convert capital names to lower case for consistency	2019-08-21 13:45:34 -07:00
Matt Guthaus	e210ef2a41	Add assert to lef and verilog unit test. Fix verilog files in golden results.	2019-01-11 16:42:50 -08:00
Matt Guthaus	a58b1906ad	Convert unit tests to scn4m_subm ... Also, fixed isdiff for python3.	2018-09-17 11:13:46 -07:00