OpenRAM

Commit Graph

Author	SHA1	Message	Date
Matt Guthaus	30fc81a1f0	Update copyright year.	2021-01-22 11:23:28 -08:00
mrg	305b546ad5	PEP8 cleanup	2020-11-17 16:56:00 -08:00
mrg	02c1fac3b8	Remove partial Verilog output	2020-11-17 16:51:08 -08:00
mrg	baae28194b	Add custom cell custom port order code. Update setup/hold to use it.	2020-11-17 11:12:59 -08:00
mrg	da721a677d	Remove EOL whitespace globally	2020-11-03 06:29:17 -08:00
mrg	88731ccd8e	Fix rounding error for wmask with various word_size	2020-09-28 09:53:01 -07:00
Matt Guthaus	289d3b3988	Feedthru port edits. Comment about write driver size for write through to work, but disable write through in functional simulation. Provide warning in Verilog about write throughs.	2019-09-27 14:18:49 -07:00
Matt Guthaus	9f54afbf2c	Fix capitalization in verilog golden files	2019-08-21 14:29:57 -07:00
Matt Guthaus	d0f04405a6	Convert capital names to lower case for consistency	2019-08-21 13:45:34 -07:00
jsowash	ad0af54a9f	Removed dupliction of addr_size.	2019-07-22 13:18:52 -07:00
jsowash	0a5461201a	Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used.	2019-07-19 14:58:37 -07:00
jsowash	5258016c9f	Changed location of port for din_reg.	2019-07-06 12:27:24 -07:00
jsowash	6fe78fe04a	Removed begin end for Verilog without wmask.	2019-07-06 11:29:34 -07:00
jsowash	24bfaa3b76	Added write_size to test 16 and added a newline to Verilog with no wmask for test 25.	2019-07-05 15:55:03 -07:00
jsowash	ad9193ad5a	Verified 1rw mask writing and changed verilog.py accordingly.	2019-07-05 15:08:59 -07:00
jsowash	125112b562	Added wmask flip flop. Need work on placement still.	2019-07-04 10:34:14 -07:00
Matt Guthaus	a234b0af88	Fix space before comment	2019-06-14 08:43:41 -07:00
Matt Guthaus	0f03553689	Update copyright to correct years.	2019-05-06 06:50:15 -07:00
Matt Guthaus	3f9a987e51	Update copyright. Add header to all OpenRAM files.	2019-04-26 12:33:53 -07:00
Matt Guthaus	20b869f8e1	Remove tabs	2019-01-11 14:16:57 -08:00
Matt Guthaus	5de7ff3773	Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.	2019-01-11 14:15:16 -08:00
Matt Guthaus	84c798d9e4	Move last few modules to base dir	2018-02-09 10:29:37 -08:00

22 Commits