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OpenRAM
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808 Commits

Author SHA1 Message Date
Matt Guthaus af84742c19 Simplify m2 pitch calculation 2018-07-09 09:57:57 -07:00
Matt Guthaus a9a95ebf7c Fix pex test permissions 2018-07-09 09:11:14 -07:00
Matt Guthaus b3dc6560f5 Remove regress.sh script 2018-07-09 09:10:12 -07:00
Matt Guthaus c19d7523c1 Merge branch 'dev' into multiport_cleanup 2018-07-06 11:02:34 -07:00
Matt Guthaus 5d32a426c4 Change test sram path so jobs can be simultaneously run. 2018-07-06 07:34:38 -07:00
Matt Guthaus 733be110a2 Add negation to return code so tests fail or pass properly. 2018-07-06 07:27:26 -07:00
Matt Guthaus 299a9432e6 Simple change to trigger pipeline regression 2018-07-05 16:44:59 -07:00
Matt Guthaus 7c6974dd08 Fix options so it is in /tmp in RAM drive 2018-07-05 16:33:26 -07:00
Matt Guthaus 3260468477 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2018-07-05 16:27:49 -07:00
Matt Guthaus 077f3f20ec Add return code for regression test 2018-07-05 16:27:47 -07:00
Matt Guthaus 60b4ebd6a0 Update full path of gitlab runner 2018-07-05 14:33:42 -07:00
Matt Guthaus 8ad503d021 Remove regress scripts from repo. 2018-07-05 14:31:31 -07:00
Matt Guthaus 6721e2d250 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2018-07-05 13:15:44 -07:00
Matt Guthaus cfc7e49727 Test change to README to test repo mirroring 2018-07-05 13:15:37 -07:00
Matt Guthaus ded87dbbe7 Add regress runner scripts 2018-07-03 11:49:29 -07:00
Matt Guthaus 68ad436f86 Add dummy gitlab ci script 2018-07-03 11:43:23 -07:00
Matt Guthaus cc815f4c33 Fix sense amp spacing after modifying index to be increment by one. 2018-06-29 15:30:17 -07:00
Matt Guthaus 52a4ba711b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2018-06-29 15:23:14 -07:00
Matt Guthaus 99fe3b87fe Remove temp file. Fixing indexing of sense amp outputs. 2018-06-29 15:22:58 -07:00
Matt Guthaus 6ac24dbf0c Fix module name for python3 2018-06-29 15:12:15 -07:00
Matt Guthaus 3de81c8a67 Close files in trim spice and delay. 2018-06-29 15:11:41 -07:00
Matt Guthaus 8d61ccbc6f Convert byte string to string. 2018-06-29 15:11:14 -07:00
Matt Guthaus 6cd1779f7b Rename pex test so that it ends with _test and will be run by regress.py. 2018-06-29 12:47:22 -07:00
Matt Guthaus 32099646cf Add back fix to revert bitcell from pbitcell. 2018-06-29 12:45:26 -07:00
Matt Guthaus a9849eff3a Merge in mtgrime's fix. 2018-06-29 12:44:26 -07:00
Michael Timothy Grimes 82eeb297dd Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-06-29 12:07:03 -07:00
Michael Timothy Grimes 721f935d66 changing pbitcell tests to revert OPTS.bitcell to bitcell after tests 2018-06-29 12:00:36 -07:00
Matt Guthaus ac7aa4537c Remove uniqe pbitcell id since it isn't needed. Convert dos EOL to unix EOL characters. Convert python2.7 to python3 in pbitcell. 2018-06-29 11:49:02 -07:00
Matt Guthaus fa17d5e7f3 Change permissions of tests to be executable so you don't have to type python each time. 2018-06-29 11:36:30 -07:00
Matt Guthaus 69921b0844 Add enclosing well to column mux. Move well contact to cell boundary. 2018-06-29 11:35:29 -07:00
Matt Guthaus d0f34b46a0 Update README with correct compiler directory structure. 2018-06-29 10:05:40 -07:00
Matt Guthaus 3becf92e7c Combine pbitcell tests into one unit test 2018-06-29 10:00:23 -07:00
Matt Guthaus df2dce2439 Fix module import names for python3. Rename parse function to something meaningful. 2018-06-29 09:45:07 -07:00
Matt Guthaus 8cee26bc8c Allow python 3.5. Make easier to revise required version. 2018-06-29 09:23:43 -07:00
Matt Guthaus 2833b706c7 Fix duplicate name check for some modules by checking if name is a substring. Allows pbitcell to pass. 2018-06-29 09:23:23 -07:00
Michael Timothy Grimes d7a024b8fc adding another important port combination to unit tests 2018-06-03 19:36:48 -07:00
Michael Timothy Grimes fea304eac1 corrected gate to contact spacing 2018-05-31 18:31:34 -07:00
Michael Timothy Grimes e19a422696 simplfying calculations in pbitcell and changing pbitcell_array_test to check different port combinations 2018-05-31 17:39:51 -07:00
Michael Timothy Grimes 9e739d67d4 python 3 changes d.iterkeys() -> iter(d.keys()) 2018-05-29 11:54:10 -07:00
Michael Timothy Grimes 8f131ddb2f commiting changes from most recent pull from dev 2018-05-22 17:30:51 -07:00
Michael Timothy Grimes 17769f27c6 small changes to pbitcell 2018-05-22 14:51:42 -07:00
Michael Timothy Grimes d8cb3653e0 changing case of pins in handmade cell_6t for freepdk45 2018-05-22 14:19:26 -07:00
Michael Timothy Grimes 766042fe69 changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit 2018-05-22 14:16:51 -07:00
Michael Timothy Grimes 5e4d4bf6cd resolved conflicts with bitcell_array after PrivateRAM merge 2018-05-22 14:12:14 -07:00
Michael Timothy Grimes b5df0cc30a Merging branch with PrivateRAM dev 2018-05-18 15:15:31 -07:00
Matt Guthaus d4cd8aff15 Change permissions of tests 2018-05-14 16:36:58 -07:00
Matt Guthaus f34c4eb7dc Convert entire OpenRAM to use python3. Works with Python 3.6. 
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
 2018-05-14 16:15:45 -07:00
Matt Guthaus 58628d7867 Merge branch 'multiport_cleanup' into dev 2018-05-11 09:23:43 -07:00
Matt Guthaus 0e35937da5 Commit local changes. Forgot what the status is. 2018-05-11 09:15:29 -07:00
Matt Guthaus b14bef3bcf Initial merge of incomplete multi-port clean with new supply routing. 2018-05-11 08:18:04 -07:00