2018-11-07 22:37:08 +01:00
|
|
|
#!/usr/bin/env python3
|
2019-04-26 21:21:50 +02:00
|
|
|
# See LICENSE for licensing information.
|
|
|
|
|
#
|
2019-06-14 17:43:41 +02:00
|
|
|
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
|
|
|
|
# of Regents for the Oklahoma Agricultural and Mechanical College
|
|
|
|
|
# (acting for and on behalf of Oklahoma State University)
|
|
|
|
|
# All rights reserved.
|
2019-04-26 21:21:50 +02:00
|
|
|
#
|
2018-11-07 22:37:08 +01:00
|
|
|
import unittest
|
2019-05-31 19:51:42 +02:00
|
|
|
from testutils import *
|
2018-11-07 22:37:08 +01:00
|
|
|
import sys,os
|
2019-05-31 19:51:42 +02:00
|
|
|
sys.path.append(os.getenv("OPENRAM_HOME"))
|
2018-11-07 22:37:08 +01:00
|
|
|
import globals
|
|
|
|
|
from globals import OPTS
|
2019-03-06 23:12:24 +01:00
|
|
|
from sram_factory import factory
|
2018-11-07 22:37:08 +01:00
|
|
|
import debug
|
|
|
|
|
|
2018-12-05 02:08:22 +01:00
|
|
|
#@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, wide metal supply routing error")
|
2018-11-07 22:37:08 +01:00
|
|
|
class psram_1bank_2mux_test(openram_test):
|
|
|
|
|
|
|
|
|
|
def runTest(self):
|
2019-03-08 19:47:41 +01:00
|
|
|
globals.init_openram("config_{0}".format(OPTS.tech_name))
|
2018-11-07 22:37:08 +01:00
|
|
|
from sram_config import sram_config
|
|
|
|
|
OPTS.bitcell = "pbitcell"
|
|
|
|
|
OPTS.replica_bitcell="replica_pbitcell"
|
2019-07-12 19:39:55 +02:00
|
|
|
OPTS.dummy_bitcell="dummy_pbitcell"
|
2018-11-07 22:37:08 +01:00
|
|
|
|
|
|
|
|
# testing layout of sram using pbitcell with 1 RW port (a 6T-cell equivalent)
|
|
|
|
|
OPTS.num_rw_ports = 1
|
|
|
|
|
OPTS.num_w_ports = 0
|
|
|
|
|
OPTS.num_r_ports = 0
|
|
|
|
|
|
|
|
|
|
c = sram_config(word_size=4,
|
|
|
|
|
num_words=32,
|
|
|
|
|
num_banks=1)
|
|
|
|
|
c.num_words=32
|
|
|
|
|
c.words_per_row=2
|
2018-12-06 22:11:47 +01:00
|
|
|
c.recompute_sizes()
|
2019-03-06 23:24:24 +01:00
|
|
|
debug.info(1, "Layout test for {}rw,{}r,{}w psram "
|
|
|
|
|
"with {} bit words, {} words, {} words per "
|
|
|
|
|
"row, {} banks".format(OPTS.num_rw_ports,
|
|
|
|
|
OPTS.num_r_ports,
|
|
|
|
|
OPTS.num_w_ports,
|
|
|
|
|
c.word_size,
|
|
|
|
|
c.num_words,
|
|
|
|
|
c.words_per_row,
|
|
|
|
|
c.num_banks))
|
2019-03-06 23:12:24 +01:00
|
|
|
a = factory.create(module_type="sram", sram_config=c)
|
2018-11-07 22:37:08 +01:00
|
|
|
self.local_check(a, final_verification=True)
|
|
|
|
|
|
|
|
|
|
globals.end_openram()
|
|
|
|
|
|
|
|
|
|
# run the test from the command line
|
|
|
|
|
if __name__ == "__main__":
|
|
|
|
|
(OPTS, args) = globals.parse_args()
|
|
|
|
|
del sys.argv[1:]
|
|
|
|
|
header(__file__, OPTS.tech_name)
|
2019-05-31 19:51:42 +02:00
|
|
|
unittest.main(testRunner=debugTestRunner())
|