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6f4994babd
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2025-05-13 10:10:02 +02:00 |
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2025-05-13 10:09:14 +02:00 |
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2025-05-13 10:07:31 +02:00 |
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change mismatch properties
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2025-05-13 10:07:15 +02:00 |
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de3fd69d92
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change mismatch notation
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2025-05-13 09:20:27 +02:00 |
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change postprocessing
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2025-05-13 09:18:20 +02:00 |
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2025-05-13 09:17:36 +02:00 |
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change mc analysis
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2025-05-13 09:10:18 +02:00 |
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change mismatch notation
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2025-05-13 08:52:41 +02:00 |
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Update design_of_bgr.md
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2025-05-13 08:50:16 +02:00 |
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2025-05-12 14:17:50 +02:00 |
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2025-05-12 13:59:40 +02:00 |
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2025-05-06 14:22:00 +02:00 |
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2025-05-06 13:51:43 +02:00 |
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forcing simulations folder into repo
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2025-05-06 13:45:14 +02:00 |
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2025-05-06 12:51:37 +02:00 |
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87b3e3b029
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remove verilogA amp
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2025-05-06 09:29:47 +02:00 |
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2025-05-06 09:13:18 +02:00 |
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change qucs-s schematic
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2025-05-05 13:18:26 +02:00 |
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restructure media
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2025-04-30 09:51:22 +02:00 |
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2025-04-22 15:55:25 +02:00 |
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2025-04-22 15:52:15 +02:00 |
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2025-04-22 15:48:26 +02:00 |
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2025-04-22 15:41:00 +02:00 |
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2025-04-22 15:40:49 +02:00 |
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2025-04-22 14:58:44 +02:00 |
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2025-04-11 09:05:29 +02:00 |
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2025-04-11 08:18:57 +02:00 |
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2025-04-11 08:18:19 +02:00 |
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2025-04-11 08:01:55 +02:00 |
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2025-04-10 16:04:26 +02:00 |
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2025-04-10 16:02:34 +02:00 |
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2025-04-10 16:02:10 +02:00 |
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Update array_comps.md
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2025-04-10 16:01:54 +02:00 |
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2025-04-10 14:38:34 +02:00 |
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2025-04-10 13:26:41 +02:00 |
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2025-04-10 13:25:25 +02:00 |
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2025-04-10 09:37:14 +02:00 |
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Update comparator.md
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2025-04-09 14:39:21 +02:00 |
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2025-04-09 14:39:08 +02:00 |
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2025-04-09 14:12:41 +02:00 |
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create media
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2025-04-09 14:09:08 +02:00 |
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f5e5b8013d
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create SAR ADC intro
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2025-04-09 11:59:17 +02:00 |
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2025-04-09 11:52:21 +02:00 |
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2025-04-09 11:49:57 +02:00 |
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Update EM_simulation.md
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2025-04-09 11:34:21 +02:00 |